Advanced bus-clamping PWM techniques based on space vector approach

Narayanan, G.; Krishnamurthy, Harish K.; Zhao, Dan; Ayyanar, Raja

doi:10.1109/tpel.2006.876854

Cited by 166 publications

(113 citation statements)

References 13 publications

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“…The PWM schemes where the dwell time of the active vector are divided into two equal intervals in each half-carrier cycle is proposed in [5], [20], [21], [34], [35]. However, the dwell time of an active vector is not divided equally in this paper.…”

Section: Modified Dpwm For Circulating Current Reductionmentioning

confidence: 99%

“…13(a). The time integral of the error vectors gives the harmonic flux vector, which is proportional to the ripple current [5], [20], [21].…”

Section: B Ripple Current Analysismentioning

confidence: 99%

“…The commutation of each phase leg is ceased for the one third period of the fundamental cycle [18], [19]. The PWM schemes, which modify the DPWM schemes by dividing one of the active vectors into two equal halves, are proposed in [20], [21]. These PWM schemes affect the line current ripple.…”

Section: Introductionmentioning

confidence: 99%

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Modified Discontinuous PWM for Size Reduction of the Circulating Current Filter in Parallel Interleaved Converters

Gohil

Maheshwari

Bede

et al. 2015

IEEE Trans. Power Electron.

106

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Suggested citation format:Gohil, G.; Maheshwari, R.; Bede, L.; Kerekes, T.; Teodorescu, R.; Liserre, M.; Blaabjerg, F., "Modified Discontinuous PWM for Size Reduction of the Circulating Current Filter in Parallel Interleaved Converters," IEEE Transactions on Power Electronics , vol.30, no.7, pp.3457,3470, July 2015. General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognize and abide by the legal requirements associated with these rights. Users may download and print one copy of any publication from the public portal for the purpose of private study or research.  You may not further distribute the material or use it for any profit-making activity or commercial gain.  You may freely distribute the URL identifying the publication in the public portal. Take down policyIf you believe that this document breaches copyright please contact us at vbn@aub.aau.dk providing details, and we will remove access to the work immediately and investigate your claim. Abstract-Parallel Voltage Source Converters (VSCs) require an inductive filter to suppress the circulating current. The size of this filter can be minimized by reducing either the maximum value of the flux linkage or the core losses. This paper presents a modified Discontinuous Pulsewidth Modulation (DPWM) scheme to reduce the maximum value of the flux linkage and the core losses in the circulating current filter. In the proposed PWM scheme, the dwell time of an active vector is divided within a half-carrier cycle to ensure simultaneous occurrence of the same zero vectors in both VSCs. A function to decide the ratio of the dwell time of the divided active vector is also presented. The effect of the proposed PWM scheme on the maximum value of the flux linkage and the core losses is analyzed and compared with that of the space vector modulation and 60• clamped DPWM schemes. The analytical expressions for the maximum value of the flux linkage are derived for each of these PWM schemes. In addition, the effect of the proposed PWM scheme on the line current ripple and the switching losses is also analyzed and compared. To verify the analysis, experimental results are presented, which prove the effectiveness of the proposed PWM scheme.

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Section: Modified Dpwm For Circulating Current Reductionmentioning

confidence: 99%

“…13(a). The time integral of the error vectors gives the harmonic flux vector, which is proportional to the ripple current [5], [20], [21].…”

Section: B Ripple Current Analysismentioning

confidence: 99%

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Modified Discontinuous PWM for Size Reduction of the Circulating Current Filter in Parallel Interleaved Converters

Gohil

Maheshwari

Bede

et al. 2015

IEEE Trans. Power Electron.

106

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“…In other words just by changing the zero state at any interval γ = α ranging from 0 0 60 0 to different DPWM methods can be generated. All the existing DPWM methods use clamping sequences 012 and 721 [5]- [7]. The so called DPWM methods popularly by the names DPWM0, DPWM1, DPWM2, and DPWM3 can be generated with this method by choosing a proper value of γ [5].…”

Section: B Proposed Adpwm Algorithmmentioning

confidence: 99%

Minimum Switching Loss ADPWM Algorithm Based DTC Induction Motor Drive Operating at Near Rated Speeds

Gowri¹,

Reddy

Babu

2009

2009 International Conference on Advances in Computing, Control, and Telecommunication Technologies

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In this paper a high performance advanced discontinuous PWM (ADPWM) algorithm for direct torque controlled (DTC) induction motor drive is proposed. The proposed ADPWM method uses a special category of DPWM sequences (0121 and 7212), because of which the performance of the drive improves in terms of the inverter switching losses. Also, significant reduction in line current distortion during high speed operations is achieved.

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“…Hence to reduce the switching losses and to improve the performance in high modulation region, several bus-clamping SV-PWM methods have been proposed [5,21,[27][28][29][30][31]. Unfortunately, those are based on the conventional SV-PWM without considering hardware resource saving.…”

Section: Introductionmentioning

confidence: 99%

Hardware-Resource Saving for Realization of Space Vector PWM Based on Fpga Using Bus-Clamping Technique

Sutikno

2009

TELKOMNIKA

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Advanced bus-clamping PWM techniques based on space vector approach

Cited by 166 publications

References 13 publications

Modified Discontinuous PWM for Size Reduction of the Circulating Current Filter in Parallel Interleaved Converters

Modified Discontinuous PWM for Size Reduction of the Circulating Current Filter in Parallel Interleaved Converters

Minimum Switching Loss ADPWM Algorithm Based DTC Induction Motor Drive Operating at Near Rated Speeds

Hardware-Resource Saving for Realization of Space Vector PWM Based on Fpga Using Bus-Clamping Technique

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