Advanced Air Gap Formation Scheme Using Volatile Material

Warashina, Hideki; Kawasaki, Hiroaki; Nagai, Hiroyuki; Yamaguchi, Tatsuya; Satô, Norio; Kikuchi, Yoshiyuki; Sun, Xin

doi:10.1109/iitc51362.2021.9537549

Cited by 5 publications

(3 citation statements)

References 4 publications

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“…A method often employed to reduce the crosstalk is fabricating air gaps using trenches, which decrease the stray capacitance between the tracks (e.g., gate electrodes) [22,23]. This can be understood as due to a reduced dielectric constant of the vacuum gap with respect to the silicon substrate.…”

Section: Resultsmentioning

confidence: 99%

Contact Pad Design Considerations for Semiconductor Qubit Devices for Reducing On-Chip Microwave Crosstalk

Tomari

Yoneda

Kodera

2023

IEICE Trans. Electron.

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Reducing on-chip microwave crosstalk is crucial for semiconductor spin qubit integration. Toward crosstalk reduction and qubit integration, we investigate on-chip microwave crosstalk for gate electrode pad designs with (i) etched trenches between contact pads or (ii) contact pads with reduced sizes. We conclude that the design with feature (ii) is advantageous for high-density integration of semiconductor qubits with small crosstalk (below -25 dB at 6 GHz), favoring the introduction of flipchip bonding.

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Section: Resultsmentioning

confidence: 99%

Contact Pad Design Considerations for Semiconductor Qubit Devices for Reducing On-Chip Microwave Crosstalk

Tomari

Yoneda

Kodera

2023

IEICE Trans. Electron.

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“…The continued miniaturization of features in integrated circuits for the development of future technology nodes will drive the half pitch of back-end-of-line (BEOL) interconnects to <10 nm, introducing significant performance and reliability challenges [ 1 , 2 , 3 , 4 ]. Despite the advances in novel low- k dielectrics and liner layer scaling, the increase in the resistance-capacitance (RC) delay poses a serious threat to the damascene Cu extendibility, which has been the industrial standard for BEOL interconnects since its introduction in 2000 [ 5 , 6 , 7 , 8 , 9 , 10 ]. This increase in the RC delay is a direct consequence of the resistivity size effect, which is primarily attributed to electron scattering at surfaces [ 11 , 12 , 13 , 14 , 15 , 16 ] and grain boundaries [ 17 , 18 , 19 , 20 , 21 ] as the linewidths w or grain size D of nanoscale conductors approach and become smaller than the electron–phonon scattering mean free path, which is 39 nm for Cu [ 22 , 23 , 24 ].…”

Section: Introductionmentioning

confidence: 99%

Anisotropic Resistivity Size Effect in Epitaxial Mo(001) and Mo(011) Layers

et al. 2023

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Mo(001) and Mo(011) layers with thickness d = 4–400 nm are sputter-deposited onto MgO(001) and α-Al2O3(112¯0) substrates and their resistivity is measured in situ and ex situ at room temperature and 77 K in order to quantify the resistivity size effect. Both Mo(001) and Mo(011) layers are epitaxial single crystals and exhibit a resistivity increase with decreasing d due to electron surface scattering that is well described by the classical Fuchs and Sondheimer model. Data fitting yields room temperature effective electron mean free paths λ*= 14.4 ± 0.3 and 11.7 ± 0.3 nm, respectively, indicating an anisotropy with a smaller resistivity size effect for the Mo(011) orientation. This is attributed to a smaller average Fermi velocity component perpendicular to (011) surfaces, causing less surface scattering and a suppressed resistivity size effect. First-principles electronic structure calculations in combination with Boltzmann transport simulations predict an orientation dependent transport with a more pronounced resistivity increase for Mo(001) than Mo(011). This is in agreement with the measurements, confirming the effect of the Fermi surface shape on the thin-film resistivity. The predicted anisotropy λ001*/λ011* = 1.57 is in reasonable agreement with 1.66 and 1.23 measured at 77 and 295 K. The overall results indicate that the resistivity size effect in Mo is relatively small, with a measured product of the bulk resistivity times the effective electron mean free path ρoλ* = (7.7 ± 0.3) and (6.2 ± 0.2) × 10−16 Ωm2 for Mo(001) and Mo(011) layers. The latter value is in excellent agreement with the first-principles-predicted ρoλ = 5.99 × 10−16 Ωm2 and is 10% and 40% smaller than the reported measured ρoλ for Cu and W, respectively, indicating the promise of Mo as an alternate conductor for narrow interconnects.

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“…On the other hand, subtractive etch scheme is flexible to design higher AR, so we can get much lower resistance [6]. If we want to increase AR for the metal line resistance reduction, we also need to implement airgap to compensate capacitance increase between metals [7].…”

mentioning

confidence: 99%

Enabling process technologies for advanced logic devices beyond FinFET era

Yamamoto

2023

Advanced Etch Technology and Process Integration for Nanopatterning XII

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This invited talk describes the enabling process technologies for advanced logic devices beyond FinFET era. Gate-all-around (GAA) improves electrostatics over FinFET and enables continuous gate length scaling. Complementary FET (CFET), which is a structure of stacked transistors, is a next candidate architecture for the continuous cell height scaling enablement. Interconnect pitch scaling will also play crucial role for it and go with RC reduction knobs such as Cu damascene extension, post Cu and airgap. For better area usage and performance enhancement, backside power delivery network (PDN) is an attractive option. For these enablement, continuous process and tool advancement is necessary not only on film, etch, lithography and wet, but also on wafer bonding and thinning technologies. We will also review our recent progress in EUV related solutions including self-aligned patterning.

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Advanced Air Gap Formation Scheme Using Volatile Material

Cited by 5 publications

References 4 publications

Contact Pad Design Considerations for Semiconductor Qubit Devices for Reducing On-Chip Microwave Crosstalk

Contact Pad Design Considerations for Semiconductor Qubit Devices for Reducing On-Chip Microwave Crosstalk

Anisotropic Resistivity Size Effect in Epitaxial Mo(001) and Mo(011) Layers

Enabling process technologies for advanced logic devices beyond FinFET era

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