Adding synchronous and LSSD modes to asynchronous circuits

Berkel, Kees van; Peeters, A.; Beest, Frank te

doi:10.1109/async.2002.1000306

Cited by 14 publications

(4 citation statements)

References 9 publications

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“…At the 21th century begin, Berkel et al explores the insertion of synchronous and LSSD modes to C-elements [18], targeting a more general testing approach of any asynchronous implementation. Here, they consider the scan-path technique and level-sensitive operation of LSSD operation to add full controllability and observability in sequential gates.…”

Section: Related Workmentioning

confidence: 99%

“…Consequently, asynchronous circuits could take advantage of traditional DfT and automatic test pattern generation (ATPG) tools. This statement is further explored in [19], [20], where it applies the DfT proposed in [18] and presents fault coverage and area results of five testable bundled-data circuits designed with Tangram, a Philips' design flow for asynchronous circuits. The authors were able to test both data and control paths with 100% and 99% fault coverage, respectivately, with area overhead ranging from 90% (full-scan) to 30% (partial-scan).…”

Section: Related Workmentioning

confidence: 99%

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At-speed DfT Architecture for Bundled-data Design

Guazzelli

Fesquet

2020

2020 IEEE International Test Conference (ITC)

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At-speed testing for asynchronous circuits is still an open concern in the literature. Due to its timing constraints between control and data paths, Design for Testability (DfT) methodologies must test both control and data paths at the same time in order to guarantee the circuit correctness. As Process Voltage Temperature (PVT) variations significantly impact circuit design in newer CMOS technologies and low-power techniques such as voltage scaling, the timing constraints between control and data paths must be tested after fabrication not only under nominal conditions but through a range of operating conditions. However, this requirement demands modifications in the control and data paths, which are not straightforward and not desirable from a commercial standpoint due to its incompatibility with conventional testing tools. Even with the available testing methodologies for asynchronous circuits in the literature -by adapting the existing techniques for synchronous or creating new ones from scratch -those methodologies usually target the control or data path. This work explores an at-speed testing approach for bundled data circuits, targeting the micropipeline template. The main target of this test approach focuses on whether the sized delay lines in control paths respect the local timing assumptions of the data paths. By adding extra controllability points in the controllers and taking advantage of scan-chain structures, this work targets to generate/stall tokens in controllers, enabling circuit verification through available scan chains.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

At-speed DfT Architecture for Bundled-data Design

Guazzelli

Fesquet

2020

2020 IEEE International Test Conference (ITC)

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“…One popular test solution is to integrate scan paths into the asynchronous design (cf. [3], [4], [5]), since this technique is established for synchronous systems and accepted by the industry. Unfortunately, introducing scan paths is a large overhead due to the integration of a clock tree that should be avoided within asynchronous designs.…”

Section: Introductionmentioning

confidence: 99%

Ultra low cost asynchronous handshake checker

Zeidler

Ehrig

Krstić

et al. 2009

2009 15th IEEE International on-Line Testing Symposium

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This paper presents a new on-line checking scheme for asynchronous handshake protocols. The proposed scheme requires very small chip area while maintaining high coverage for all considered faults which are briefly exposed. In addition to simple pass-fail information the checker provides off-line diagnosis capabilities in order to further analyze the cause of a fault and the time of its occurrence. In order to verify its functionality the checker was proven by performing analogue simulations. In addition the area overhead and the power consumption was determined and compared with existing implementations.

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“…Generally, the design for testability (DFT) of synchronous digital systems is based on the scan chain approach. There are similar techniques also in asynchronous domain [1]. On the other hand, there are claims that a functional test is sufficiently effective for asynchronous circuits.…”

Section: Introductionmentioning

confidence: 93%

BIST Technique for GALS Systems

Krstić

Grass

8th Euromicro Conference on Digital System Design (DSD'05)

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In this paper a test technique based on the Built-In SelfTest (BIST) is proposed. Our BIST concept is based on hierarchical testing of the digital systems. The presented test scheme is optimized for Globally Asynchronous Locally Synchronous (GALS) systems. The BIST technique, described here, is implemented on a GALS baseband processor compliant to the IEEE 802.11a standard. Some results on the performance of our test solution are given. The GALS processor with embedded BIST was fabricated in IHP's 0.25 µm CMOS technology and test results are presented.

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Adding synchronous and LSSD modes to asynchronous circuits

Cited by 14 publications

References 9 publications

At-speed DfT Architecture for Bundled-data Design

At-speed DfT Architecture for Bundled-data Design

Ultra low cost asynchronous handshake checker

BIST Technique for GALS Systems

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