Adding a vector unit to a superscalar processor

Abstract

The focus of this paper is on adding a vector unit to a superscalar core, as a way to scale current state of the art superscalar processors.The proposed architecture has a vector register file that shares functional units both with the integer datapath and with the floatingpoint datapath. A key point in our proposal is the design of a high performance cache interface that delivers high bandwidth to the vector unit at a low cost and low latency. We propose a double-banked cache with alignment circuitry to serve vector accesses and we study two cache hierarchies: one feeds the uector unit from the Ll; the other from the L.2. Our results show that large IPC values (higher than IO in some cases) can be achieved. Moreover the scalability of our architecture simply requires addition of functional units, without requiring more issue bandwidth. As a consequence, the proposed vector unit achieves high performance for numerical and multimedia codes with minimal impact on the cycle time of the processor or on the performance of integer codes.

On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications

“…Parameters are similar to those found in some recent microprocessors with multimedia extensions like PowerPC970. For VMMX versions a vector cache was used [22]. The vector cache is a twobank interleaved cache targeted at accessing stride-one vector requests by loading two whole cache lines (one per bank) instead of individually loading the vector elements.…”

Exploiting a new level of DLP in multimedia applications

“…The correctness of the output was verified to ensure no visually perceptible losses in accuracy. Finally, we modified our Jinks simulator [10] to be able to filter the input instruction stream provided by ATOM [15] and correctly simulate the emulated instructions.…”

“…In [10], we studied the design of cost-effective cache hierarchies to leverage high-bandwidth for out-of-order vector processors. In the same way as conventional vector instructions, MOM memory patterns have the potential to allow a smart exploitation of the spatial locality intrinsic in multimedia codes.…”

“…The vector cache was proposed in [10] and heavily borrows from the ideas introduced in [20]. As it can be seen in figure 6, the vector cache is targeted at accessing stride-one vector requests by loading two whole cache lines (one per interleaved bank) instead of individually loading the vector elements.…”

“…Recent works dealing with the DLP exploitation of multimedia applications can be divided into two different groups: those evaluating the performance of conventional vector ISAs on multimedia codes [9,10], and those evaluating the performance of current multimedia extensions [11,12].…”