ADC Resolution for Simultaneous Reception of Two Signals with High Dynamic Range

Laporte-Fauret, Baptiste; Ferré, Guillaume; Dallet, Dominique; Minger, Bryce; Fuché, Loïc

doi:10.1109/icecs.2018.8617945

Cited by 5 publications

(3 citation statements)

References 6 publications

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“…In order to determine system-level parameters, Matlab modeling of proposed hybrid ADC structure is carried out. According to formula (1), provided that the VFS,1 and VFS,2 are equivalent to 1800 mV (differential value), while G and R as well as N are 32 times, 2 bit and 16 bit. Figure 1c shows the equivalent quantization error (QE) of two-step pipelined-SAR ADC versus the resolution of first- In order to determine system-level parameters, Matlab modeling of proposed hybrid ADC structure is carried out.…”

Section: The Proposed Architecture Modeling Of Adcmentioning

confidence: 99%

“…Figure 1c shows the equivalent quantization error (QE) of two-step pipelined-SAR ADC versus the resolution of first- In order to determine system-level parameters, Matlab modeling of proposed hybrid ADC structure is carried out. According to formula (1), provided that the V FS,1 and V FS,2 are equivalent to 1800 mV (differential value), while G and R as well as N are 32 times, 2 bit and 16 bit. Figure 1c shows the equivalent quantization error (QE) of two-step pipelined-SAR ADC versus the resolution of first-stage SAR ADC and second-stage SAR ADC w/ or w/o ISDM assisted by the Matlab modeling.…”

Section: The Proposed Architecture Modeling Of Adcmentioning

confidence: 99%

“…High resolution analog-to-digital converters (ADCs) have been widely used in the medical imaging, radar and high precision industrial control, where it exists a pressing need for power efficient ADCs operating at tens of mega-samples per second (MSPS) [1][2][3]. The successive approximation register (SAR) ADCs have an advantage of power efficiency because of their simple configuration and digitally oriented character that utilize high-speed and low-power CMOS process [4].…”

Section: Introductionmentioning

confidence: 99%

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Modeling of High-Resolution Data Converter: Two-Step Pipelined-SAR ADC based on ISDM

Gao

Sun

et al. 2020

Electronics

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The features of high-resolution and high-bandwidth are in an increasing demand considering to the wide range application fields based on high performance data converters. In this paper, a modeling of high-resolution hybrid analog-to-digital converter (ADC) is proposed to meet those requirements, and a 16-bit two-step pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with first-order continuous-time incremental sigma-delta modulator (ISDM) assisted is presented to verify this modeling. The combination of high-bandwidth two-step pipelined-SAR ADC with low noise ISDM and background comparator offset calibration can achieve higher signal-to-noise ratio (SNR) without sacrificing the speed and plenty of hardware. The usage of a sub-ranging scheme consists of a coarse SAR ADC followed by an fine ISDM, can not only provide better suppression of the noise added in 2nd stage during conversion but also alleviate the demands of comparator’s resolution in both stages for a given power budget, compared with a conventional Pipelined-SAR ADC. At 1.2 V/1.8 V supply, 33.3 MS/s and 16 MHz input sinusoidal signal in the 40 nm complementary metal oxide semiconductor (CMOS) process, the post-layout simulation results show that the proposed hybrid ADC achieves a signal-to-noise distortion ratio (SNDR) and a spurious free dynamic range (SFDR) of 86.3 dB and 102.5 dBc respectively with a total power consumption of 19.2 mW.

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Section: The Proposed Architecture Modeling Of Adcmentioning

confidence: 99%

Section: The Proposed Architecture Modeling Of Adcmentioning

confidence: 99%