Adaptive Viterbi decoding of convolutional codes over memoryless channels

Chan, François; Haccoun, D.

doi:10.1109/26.649755

Cited by 79 publications

(46 citation statements)

References 7 publications

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“…A simple change of the input configuration of the simple GDI cell corresponds to very different Boolean functions [6]. This GDIL undoubtedly reduces area as lesser number of LUTs and CLBs are used in FPGA prototyping [7].…”

Section: Gdil Based Viterbimentioning

confidence: 99%

Virtex 4 FPGA Implementation of Viterbi Decoded 64-bit RISC for High Speed Application using Xilinx

Dutta¹,

Mast²

2014

IJCA

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In the modern era of electronics and communication decoding and encoding of any data(s) using VLSI technology requires low power, less area and high speed constrains. The viterbi decoder using survivor path with necessary parameters for wireless communication is an attempt to reduce the power and cost and at the same time increase the speed compared to normal decoder. This paper presents three objectives. Firstly, an orthodox viterbi decoder is designed and simulated. For faster process application, the Gate Diffused Input Logic (GDIL) based viterbi decoder is designed using Xilinx ISE, simulated and synthesized successfully. The new proposed GDIL viterbi provides very less path delay with low power simulation results. Secondly, the GDIL viterbi is again compared with our proposed technique, which comprises a Survivor Path Unit (SPU) implements a trace back method with DRAM. This proposed approach of incorporating DRAM stores the path information in a manner which allows fast read access without requiring physical partitioning of the DRAM. This leads to a comprehensive gain in speed with low power effects. Thirdly, all the viterbi decoders are compared, simulated, synthesized and the proposed approach shows the best simulation and synthesize results for low power and high speed application in VLSI design. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder(s) have been operated in deep pipelined manner to achieve high transmission rate. Although the register exchange based survivor unit has better throughput when compared to trace back unit, but in this paper by introducing the RAM cell between the ACS array and output register bank, a significant amount of reduction in path delay has been observed. All the designing of viterbi is done using Xilinx ISE 12.4 and synthesized successfully in the FPGA Virtex 4 target device operated at 64.516 MHz clock frequency, reduces almost 41% of total path delay.

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Section: Gdil Based Viterbimentioning

confidence: 99%

Virtex 4 FPGA Implementation of Viterbi Decoded 64-bit RISC for High Speed Application using Xilinx

Dutta¹,

Mast²

2014

IJCA

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“…As convolutional codes become more powerful, Power Consumption Ratio Figure 15 Power consumption ratio of phong shading and gouraud shading: one triangle shading the complexity of the corresponding decoders generally increases. The Viterbi algorithm (VA) [16,17], which is the most extensively employed decoding algorithm for convolutional codes, works well for codes with short constraint length K. For more powerful codes with large constraint lengths the Adaptive Viterbi algorithm (AVA) [18,19] is used. It reduces the average number of computations per decoded information bit.…”

Section: Adaptive Viterbi Decodingmentioning

confidence: 99%

Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations

Jain

Laffely

Burleson

et al. 2004

The Journal of VLSI Signal Processing-Systems for Signal, Image

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Signal processing algorithms and architectures can use dynamic reconfiguration to exploit variations in signal statistics with the objectives of improved performance and reduced power. Parameters provide a simple and formal way to characterize incremental changes to a computation and its computing mechanism. This paper develops a framework for dynamic parameterization and applies it to MPEG-4 motion estimation.A novel motion estimation architecture facilitates the dynamic variation of parameters to achieve power-compression tradeoffs. Our work shows that parameter variation in motion estimation helps achieve power reduction by an order of magnitude, trading off higher ii

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“…In Adaptive Viterbi Algorithms (AVA), developed in [7][8][9], the decoding performance is increased by reducing the number of operations required to decode a single bit. This is achieved by reducing truncation length (TL) or by reducing the number of survivor paths¸ i.e., those paths that are kept in order to find the optimum path.…”

Section: Receiver Energy Modelmentioning

confidence: 99%

A game theoretic approach to dynamic energy minimization in wireless transceivers

Iranli¹,

Fatemi²,

Pedram³

2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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Adaptive Viterbi decoding of convolutional codes over memoryless channels

Cited by 79 publications

References 7 publications

Virtex 4 FPGA Implementation of Viterbi Decoded 64-bit RISC for High Speed Application using Xilinx

Virtex 4 FPGA Implementation of Viterbi Decoded 64-bit RISC for High Speed Application using Xilinx

Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations

A game theoretic approach to dynamic energy minimization in wireless transceivers

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