Adaptive test clock scheme for low transition LFSR and external scan based testing

Sivanantham, S.; Gopakumar, G.; Pandey, A.R.; Paikada, M. J.

doi:10.1109/iccci.2013.6466280

Cited by 4 publications

(3 citation statements)

References 13 publications

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“…Now when the clock changes back to 1, Q still remains unaffected by the changes in D because it is now hindered by the second level of pass transistor. Thus we observe that Q remains unchanged for the entire clock cycle and changes only at the positive edge [15]. Hence the above transistor level diagram implements positive edge trigger flip flop.…”

Section: Methodsmentioning

confidence: 66%

Design and Analysis of CMOS Linear Feedback Shift Registers for Low Power Application

Rosly

Reaz

Kamal

et al. 2016

AMM

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Chip manufacturing technologies have been a key to the growth in all electronics devices over the past decade, bringing added convenience and accessibility through advantages in cost, size, and power consumption. Using recent CMOS technology, LFSR is implemented until layout level which develops low power application. One of the most frequent uses of a LFSR inside a FPGA is as a counter. Using a LFSR instead of a binary counter can increase the clock rate considerably due to the low routing resource required to produce the next state logic. This paper explores the LFSR using different architecture in a 0.18μm CMOS technology. There are 3 type architecture implemented into LFSR which is NAND gates, pass transistor and transmission gates. Those LFSR are compare in term of CMOS layout, hardware implementation and power consumption using Mentor Graphics tools. Thus, it provides analysis of LFSR for low power application in CMOS VLSI.

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Section: Methodsmentioning

confidence: 66%

Design and Analysis of CMOS Linear Feedback Shift Registers for Low Power Application

Rosly

Reaz

Kamal

et al. 2016

AMM

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“…Ward et al [7] describe a compression scheme which combines linear decompressor with a non-linear decoder to provide a very high level of compression for test data. A technique for simultaneous reduction of both test data volume and test power named linear decompressor based test compression were presented in [8]. This scheme divides the test cubes into two blocks, test cube with low toggles and high toggles which feeds the scan-chain with novel DFT architecture to reduce the scan-in transitions.…”

Section: Introductionmentioning

confidence: 99%

“…Several Huffman based compression techniques such as variable-input Huffman coding, variable-to-variable Huffman coding, optimal selective Huffman coding, complementary Huffman coding and run-length based Huffman coding (RLHC) available to improve the compression efficiency, area overhead and the test application time [37]. Many low-power compression techniques are available in the literature for the minimization of test power, test data volume and test time [8,[33][34][35]. In observation-oriented test pattern generation with the scan-chain disabling technique, the test pattern generation process is assisted by testability analysis to generate the observation-oriented test patterns.…”

Section: Introductionmentioning

confidence: 99%

Test Data Compression with Alternating Equal-Run-Length Coding

Sivanantham¹,

S²,

Ramki³

et al. 2018

IJET

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This paper presents a new X-filling algorithm for test power reduction and a novel encoding technique for test data compression in scan-based VLSI testing. The proposed encoding technique focuses on replacing redundant runs of the equal-run-length vector with a shorter codeword. The effectiveness of this compression method depends on a number of repeated runs occur in the fully specified test set. In order to maximize the repeated runs with equal run length, the unspecified bits in the test cubes are filled with the proposed technique called alternating equal-run-length (AERL) filling. The resultant test data are compressed using the proposed alternating equal-run-length coding to reduce the test data volume. Efficient decompression architecture is also presented to decode the original data with lesser area overhead and power. Experimental results obtained from larger ISCAS'89 benchmark circuits show the efficiency of the proposed work. The AERL achieves up to 82.05 % of compression ratio as well as up to 39.81% and 93.20 % of peak and average-power transitions in scan-in mode during IC testing.

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