Adaptive sprinting: How to get the most out of Phase Change based passive cooling

Abstract

CMOS scaling trends lead to elevated on-chip temperatures, which substantially limit the performance of to day's processors. To improve thermal efficiency, Phase Change Materials (PCMs) have recently been used as passive cooling solutions. PCMs store large amount of heat at near-constant temperature during phase change, allowing strategies such as computational sprinting. While existing sprinting methods al low short performance boosts, there is significant unexplored potential in improving performance on systems with PCM enhanced cooling. To this end, this paper proposes a novel run time management policy driven by observations that are not captured by prior techniques: (i) PCM melts non-uniformly due to spatially heterogeneous on-chip heat distribution; (ii) power consumption during sprinting is highly application dependent and assuming a fixed sprinting power leads to lower thermal efficiency; (iii) if we monitor the remaining PCM energy at various locations, we can utilize the PCM heat storage capability much more efficiently. Theproposed Adaptive Sprinting policy exploits these observations to extend sprinting duration for increased performance gains. Our policy monitors the remaining PCM energy corresponding to each core at run time, and using this information, it decides on the number, the location and the voltage-frequency (V If) setting of the sprinting cores. Experimental evaluation including a detailed phase change thermal model demonstrates 29% performance im provement, 22% energy savings, and 43% energy delay product (EDP) reduction on average, compared to prior strategies.

DTaPO: Dynamic Thermal-Aware Performance Optimization for Dark Silicon Many-Core Systems

“…Another DVFS technique to improve dark silicon many-core systems' performance is by increasing cores' frequencies for a short period. This technique is called computation sprinting [7,11,[21][22][23][24][25][26][27]. Raghavan et al [11] proposed a computational sprinting technique to improve many-core system performance through activating all cores (including dark cores) with maximum frequency for a sub-second period to improve parallel computation and later deactivate them to cool down the chip.…”