Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses

Abstract

The design of cache memories is a crucial part of the design cycle of a modern processor, since they are able to bridge the performance gap between the processor and the memory. Unfortunately, caches with low degrees of associativity suffer a large amount of conflict misses. Although by increasing their associativity a significant fraction of these misses can be removed, this comes at a high cost in both power, area, and access time. In this work, we address the problem of high number of conflict misses in low-associative caches, by proposing an indexing policy that adaptively selects the bits from the block address used to index the cache. The basic premise of this work is that the non-uniformity in the set usage is caused by a poor selection of the indexing bits. Instead, by selecting at run time those bits that disperse the working set more evenly across the available sets, a large fraction of the conflict misses (85 percent, on average) can be removed. This leads to IPC improvements of 10.9 percent for the SPEC CPU2006 benchmark suite. By having less accesses in the L2 cache, our proposal also reduces the energy consumption of the cache hierarchy by 13.2 percent. These benefits come with a negligible area overhead.

A Review of Techniques for Optimizing Cache Energy Efficiency

“…It reduces the mapping between the tag and data. In this [8] an architectural technique have been proposed in which that is based on the hypothesis of same distribution of the least significant bit in the cache set associatively.…”

“…In [12] reduce the cache access time that also helpful in reducing the energy. In the [13] presents a technique for heavy amount of cache set-associative that use the bloom [7] hypothesis base architecture [8] TLB Index-Based [9] Way-Halting cache filters [10] Reduce the number of cache access Selective cache way [11] reduce the access time [12] set-associative cache use the bloom filters [13] bloom filter [14] PS-cache architecture [15] Hybrid cache architecture data-aware hybrid STT-RAM/SRAM cache architecture [19] NVM [20] prediction hybrid architecture [23] Other technique MultiCopy Cache (MC2) architecture [22] Filters that decrease the dynamic power by eliminating those cache ways that are not have the requested data as the bloom filters. [14] Presents another bloom filter that reduces the complexity and also reduces the access ways.…”

The Tag Filter Cache: An Energy-Efficient Approach

“…The PS-Cache has been also implemented and compared quantitatively against our TF-Cache. Finally, other recently proposed techniques focus on reducing both leakage and dynamic consumption, for example, by reducing the area of the cache tags, like in the TLB Index-Based Tagging [12], by employing direct mapped caches along with mechanisms to remove conflict misses, like in ASCIB [18], or by performing run-time partitioning, like in the Cooperative Caching scheme [19] or in the ReCaC scheme [11].…”

Dynamic associative caches: Reducing dynamic energy of first level caches

“…A technique to dynamically adjust the cache index bits to minimize conflict misses in a direct-mapped cache was proposed in [10]. The Balanced cache design [15] widens the decoder length and incorporates programmable address decoders to similarly achieve a more balanced distribution of accesses across the lines of a direct-mapped cache.…”