Adaptive R-Peak Detector in Extreme Noise Using EMD Selective Analyzer

Abderahman, Huthaifa N.; Dajani, Hilmi R.; Groza, Voicu

doi:10.1109/memea54994.2022.9856531

Cited by 2 publications

(1 citation statement)

References 36 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For instance, if we have computed the thresholds utilizing only tapes 100, 101, 103, 113, 115, 122, 123, our circuit performance would be over 99.9 (%) for selectiveness (Se) and positive predictivity (P + ), and less than 0.1 (%) for failed detection (F d ). Also, other works, such as [12] only use real data directly acquired by their own systems which makes unfeasible a fair comparison. On the other hand, we do have some works, such as in [13], which present better results than ours, even for the whole set of MIT-BIH tapes.…”

Section: A Mit-bih Comparison Between Algorithmsmentioning

confidence: 99%

A Low Power R-peak Detector Clocked at Signal Sampling Rate

Dutra,

H. C. Ferreira,

D. Colletta

et al. 2024

JICS

View full text Add to dashboard Cite

This paper presents a real-time, low-power R-peak detector implemented in an FPGA. It is different from other implementations as it runs at the same signal sampling rate, rather than utilizing a high clock frequency as utilized in batch processing with high throughput systems. Such implementation relies on a Savitzky-Golay filter for power line noise filtering, and on an adapted version of the Difference Operation Method (DOM) algorithm. The modification in DOM is needed in order to be able to process the data either without increasing the clock to process data in a batch fashion or unsustainably increasing latency. It uses the Savitzky-Golay Digital Differentiator, eliminating further filtering stages. The prototype was characterized using both the MIT-BIH database and Fluke Prosim 8 Vital Signal Simulator. The proposed system features a high degree of matched R-peaks even being extremely efficient regarding power dissipation. Moreover, it shows similar performance when compared to the original Difference Operation Method implementation.The whole system consumes 260- uW operating at 192-Hz in an FPGA model 10M50DAF484C7G, which belongs to the MAX10 family of Altera devices.

show abstract

Section: A Mit-bih Comparison Between Algorithmsmentioning

confidence: 99%