Adaptive integration of hardware and software lock elision techniques

Dice, Dave; Kogan, Alex; Lev, Yossi; Merrifield, Timothy; Moir, Mark

doi:10.1145/2612669.2612696

Cited by 30 publications

(11 citation statements)

References 10 publications

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“…Since our implementation of ALE uses GCC TM, the transformation is automated by the GCC that generates the necessary code paths and instrumentations. Our first comparisons of ALE to the original Kyoto CacheDB showed that the original read-write lock is a performance bottleneck, which concurs with the results of [13]. We also found that Kyoto performs an excessive amount of explicit thread context switches due to the specific implementation of reader-writer spin locks in the Linux pthreads library.…”

Section: Kyotocabinetsupporting

confidence: 85%

“…Afek, Matveev and Shavit [4] proposed PLE, an all-software version of HLE for read-write locks that uses a fully pessimistic STM, but still has software-software concurrency that results in using the expensive quiescence mechanism [10,21,22]. A recent paper by Dice et al [13] proposes to integrate both hardware and software into an adaptive scheme, but has a software mode that has software-software concurrency as well, and proposes manual code modifications to avoid software costs.…”

Section: Recent Work Bymentioning

confidence: 99%

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Amalgamated Lock-Elision

Afek¹,

Matveev²,

Moll³

et al. 2015

Lecture Notes in Computer Science

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Hardware lock-elision (HLE) introduces concurrency into legacy lockbased code by optimistically executing critical sections in a fast-path as hardware transactions. Its main limitation is that in case of repeated aborts, it reverts to a fallback-path that acquires a serial lock. This fallback-path lacks hardwaresoftware concurrency, because all fast-path hardware transactions abort and wait for the completion of the fallback. Software lock elision has no such limitation, but the overheads incurred are simply too high. We propose amalgamated lock-elision (ALE), a novel lock-elision algorithm that provides hardware-software concurrency and efficiency: the fallback-path executes concurrently with fast-path hardware transactions, while the common-path fast-path reads incur no overheads and proceed without any instrumentation. The key idea in ALE is to use a sequence of fine-grained locks in the fallback-path to detect conflicts with the fast-path, and at the same time reduce the costs of these locks by executing the fallback-path as a series segments, where each segment is a dynamic length short hardware transaction. We implemented ALE into GCC and tested the new system on Intel Haswell 16-way chip that provides hardware transactions. We benchmarked linked-lists, hash-tables and red-black trees, as well as converting KyotoCacheDB to use ALE in GCC, and all show that ALE significantly outperforms HLE.

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Section: Kyotocabinetsupporting

confidence: 85%

Section: Recent Work Bymentioning

confidence: 99%

Amalgamated Lock-Elision

Afek¹,

Matveev²,

Moll³

et al. 2015

Lecture Notes in Computer Science

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show abstract

“…We conducted a performance analysis of Kyoto Cache DB and concur with [9] that the global reader-writer lock is indeed the problem. However, we also found that Kyoto performs an excessive amount of thread context switches due to the specific implementation of reader-writer spin locks in the Linux pthreads library.…”

Section: % Updatessupporting

confidence: 52%

“…However, Kyoto fails to scale with increasing numbers of threads, and in fact it usually collapses after 3-4 threads. Recent work by Dice et al [9] observed a scalability bottleneck and indicated that the problem is the global reader-writer lock that Kyoto uses to synchronize database operations.…”

Section: % Updatesmentioning

confidence: 99%

Read-log-update

Matveev

Shavit

Felber

et al. 2015

Proceedings of the 25th Symposium on Operating Systems Principles

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This paper introduces read-log-update (RLU), a novel extension of the popular read-copy-update (RCU) synchronization mechanism that supports scalability of concurrent code by allowing unsynchronized sequences of reads to execute concurrently with updates. RLU overcomes the major limitations of RCU by allowing, for the first time, concurrency of reads with multiple writers, and providing automation that eliminates most of the programming difficulty associated with RCU programming. At the core of the RLU design is a logging and coordination mechanism inspired by software transactional memory algorithms. In a collection of microbenchmarks in both the kernel and user space, we show that RLU both simplifies the code and matches or improves on the performance of RCU. As an example of its power, we show how it readily scales the performance of a real-world application, Kyoto Cabinet, a truly difficult concurrent programming feat to attempt in general, and in particular with classic RCU.

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“…Finally, recent works [8,4] have investigated the use of online profiling and optimization techniques in a similar spirit to what Seer does, but for a different, complementary purpose: decide the best software fall-back and retry policies.…”

Section: Related Workmentioning

confidence: 99%

Seer

Diegues

Romano

Garbatov

2015

Proceedings of the 27th ACM Symposium on Parallelism in Algorithms and Architectures

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Scheduling concurrent transactions to minimize contention is a well known technique in the Transactional Memory (TM) literature, which was largely investigated in the context of software TMs. However, the recent advent of Hardware Transactional Memory (HTM), and its inherently restricted nature, pose new technical challenges that prevent the adoption of existing schedulers: unlike software implementations of TM, existing HTMs provide no information on which data item or contending transaction caused abort.We propose Seer, a scheduler that addresses precisely this restriction of HTM by leveraging on an on-line probabilistic inference technique that identifies the most likely conflict relations, and establishes a dynamic locking scheme to serialize transactions in a fine-grained manner. Our evaluation shows that Seer improves the performance of the Intel TSX HTM by up to 2.5×, and by 62% on average, in TM benchmarks with 8 threads. These performance gains are not only a consequence of the reduced aborts, but also of the reduced activation of the HTM's pessimistic fall-back path.

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Adaptive integration of hardware and software lock elision techniques

Cited by 30 publications

References 10 publications

Amalgamated Lock-Elision

Amalgamated Lock-Elision

Read-log-update

Seer

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