Adaptive ILP control to increase fault tolerance for VLIW processors

Sartor, Anderson L.; Wong, Stephan; Beck, Antonio Carlos Schneider

doi:10.1109/asap.2016.7760767

Cited by 12 publications

(12 citation statements)

References 32 publications

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“…We perform experiments by applying two fault tolerance techniques: duplication and triplication of the instructions. NEDA is compared with a state of the art approach named adaptive duplication with ILP reduction [6], [7]. A simulation tool has been developed to calculate the execution cycles in order to estimate the performance of all approaches, from the extracted traces of the processor execution instruction sequence.…”

Section: Resultsmentioning

confidence: 99%

“…Fig. 1b shows the approach of existing techniques, similar to [6], where the dark gray boxes depict the duplicated instructions. The latter are executed only by the coupled pipeline.…”

Section: Introductionmentioning

confidence: 99%

“…To meet the limited system resources, hardware approaches perform the instruction replication and scheduling at run-time. However, existing approaches [6], [7] explore the idle slots only inside the current instruction bundle, without exploring next instruction bundles. As a result, unnecessary time slots are added even if the idle slots of the next bundle could be used, leading to a more spare schedule and to performance degradation.…”

mentioning

confidence: 99%

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NEDA: NOP Exploitation with Dependency Awareness for Reliable VLIW Processors

Psiakis

Kritikakou

Sentieys

2017

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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International audienceCritical applications require reliable processors that combine performance with low cost and energy consumption. Very Long Instruction Word (VLIW) processors have inherent resource redundancy not constantly used due to application's fluctuating Instruction Level Parallelism (ILP). Reliability through idle slots utilization is explored either at compile-time, increasing code size and storage requirements, or at run-time only inside the current instruction bundle, adding unnecessary time slots and degrading performance. To address this issue, we propose a technique to explore the idle slots inside and across original and replicated instruction bundles reclaiming more efficiently the idle slots and creating a compact schedule. To achieve this, a dependency analysis is applied at run-time. The execution of both original and replicated instructions is allowed at any adequate function unit, providing higher flexibility on instruction scheduling. The proposed technique achieves up to 26% reduction in performance degradation over existing approaches

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Section: Resultsmentioning

confidence: 99%

“…Fig. 1b shows the approach of existing techniques, similar to [6], where the dark gray boxes depict the duplicated instructions. The latter are executed only by the coupled pipeline.…”

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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NEDA: NOP Exploitation with Dependency Awareness for Reliable VLIW Processors

Psiakis

Kritikakou

Sentieys

2017

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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“…Hardware-based approaches duplicate the instructions at runtime using specific hardware using the compiler's result. To do so, coupling of the VLIW pipelines is applied [4], [13]. When the duplicated instructions do not fit in the current bundle, an additional time slot is added.…”

Section: Related Workmentioning

confidence: 99%

“…Such approaches can be implemented either in software or in hardware. Softwarebased approaches replicate and schedule the instructions at design-time [3] and thus increase the code size, the storage needs and the power consumption compared with hardware approaches, which perform the duplication at run-time [4]. However, when permanent errors also exist, these approaches cannot be applied as they do not modify the execution of the program to exclude faulty parts.…”

Section: Introductionmentioning

confidence: 99%

Run-time Instruction Replication for permanent and soft error mitigation in VLIW processors

Psiakis

Kritikakou

Sentieys

2017

2017 15th IEEE International New Circuits and Systems Conference (NEWCAS)

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Error occurrence in embedded systems has significantly increased. Although inherent resource redundancy exist in processors, such as in Very Long Instruction Word (VLIW) processors, it is not always used due to low application's Instruction Level Parallelism (ILP). Approaches benefit the additional resources to provide fault tolerance. When permanent and soft errors coexist, spare units have to be used or the executed program has to be modified through self-repair or by using several stored versions. However, these solutions introduce high area overhead for the additional resources, time overhead for the execution of the repair algorithm and storage overhead of the multiversioning. To address these limitations, a hardware mechanism is proposed which at run-time replicates the instructions and schedules them at the idle slots considering the resource constraints. If a resource becomes faulty, the proposed approach efficiently rebinds both the original and replicated instructions during execution. In this way, the area overhead is reduced, as no spare resources are used, whereas time and storage overhead are not required. Results show up to 49% performance gain over existing techniques.

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