Adaptive Global Elimination Algorithm for Low Power Motion Estimation

Gupte, Ajit; Bharadwaj, Aprameya

doi:10.1166/jolpe.2009.1010

Cited by 4 publications

(3 citation statements)

References 20 publications

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“…The number and nature of low level operations can also be adapted dynamically to optimize power consumption. As an example, in a video encoder application, the number of computations for motion estimation is adapted for each macro-block [21]. Motion estimation is performed by comparing a macro-block with all macro-blocks in a reference frame, within a search window of size ±32 pixels.…”

Section: Adaptive Hardware Usagementioning

confidence: 99%

“…But when the macro-block is from a portion of the image with uniform background, like a wall for instance, then reducing the number of partitions doesn't compromise compression quality. This motivates an adaptive partitioning scheme, where an analysis of the macro-block indicates how fine to partition the macro-block [21]. Hadamard transform coefficients, along with the pixel variances for the macro-block are used to come up with the optimal partition.…”

Section: Adaptive Hardware Usagementioning

confidence: 99%

“…Finally the partitions to the right and bottom are all smaller with size 4 × 4 pixels, ensuring that the edge doesn't get smeared out across the partitions. Table 2 shows the relative savings in the computations and power of the adaptive partitioning scheme [21] when compared to a fixed partitioning scheme of 4 × 4 partitions [22]. The second entry indicates a power increase using this technique, even though the number of computations is reduced.…”

Section: Adaptive Hardware Usagementioning

confidence: 99%

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Adaptative Techniques to Reduce Power in Digital Circuits

Bharadwaj

Mehta

Dwivedi

et al. 2011

JLPEA

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CMOS chips are engineered with sufficient performance margins to ensure that they meet the target performance under worst case operating conditions. Consequently, excess power is consumed for most cases when the operating conditions are more benign. This article will review a suite of dynamic power minimization techniques, which have been recently developed to reduce power consumption based on actual operating conditions. We will discuss commonly used techniques like Dynamic Power Switching (DPS), Dynamic Voltage and Frequency Scaling (DVS and DVFS) and Adaptive Voltage Scaling (AVS). Recent efforts to extend these to cover threshold voltage adaptation via Dynamic Voltage and Threshold Scaling (DVTS) will also be presented. Computation rate is also adapted to actual work load requirements via dynamically changing the hardware parallelism or by controlling the number of operations performed. These will be explained with some examples from the application domains of media and wireless signal processing

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Section: Adaptive Hardware Usagementioning

confidence: 99%

Section: Adaptive Hardware Usagementioning

confidence: 99%

Section: Adaptive Hardware Usagementioning

confidence: 99%

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Adaptative Techniques to Reduce Power in Digital Circuits

Bharadwaj

Mehta

Dwivedi

et al. 2011

JLPEA

Self Cite

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ERA: An Efficient Routing Algorithm for Power, Throughput and Latency in Network-on-Chips

Sharma

Agarwal

Gaur

et al. 2010

Lecture Notes in Computer Science

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Network-on-Chip (NoC) is viewed as a viable substitution for traditional interconnection networks to achieve high performance, communication efficiency and reliability in complex VLSI architectures at deep sub micron. Achieving high performance, power efficiency with optimum area is a target for any routing algorithm in NoC. In this paper, we propose a novel routing scheme named 'ERA', which offers higher throughput with controlled delays while remaining power aware. ERA is an adaptive routing algorithm, which avoids congestion and tends to minimize the hot spots in the network. Unlike other existing algorithms, the proposed algorithm does not require any virtual channels to avoid deadlocks. We compare our algorithm with XY and OE on the basis of a performance metric called 'power performance factor' for different traffic patterns and injection models. Our results show that ERA performs better than these two algorithms.

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Optical Packet Switch Based on Dynamic Pump Wavelength Selection

Kitsuwan

Oki

2011

J. Opt. Commun. Netw.

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Adaptive Global Elimination Algorithm for Low Power Motion Estimation

Cited by 4 publications

References 20 publications

Adaptative Techniques to Reduce Power in Digital Circuits

Adaptative Techniques to Reduce Power in Digital Circuits

ERA: An Efficient Routing Algorithm for Power, Throughput and Latency in Network-on-Chips

Optical Packet Switch Based on Dynamic Pump Wavelength Selection

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