Adaptive Configuration Selection for Power-Constrained Heterogeneous Systems

Bailey, Peter E.; Lowenthal, David K.; Ravi, Vignesh T.; Rountree, Barry; Schulz, Martin; Supinski, Bronis R. de

doi:10.1109/icpp.2014.46

Cited by 43 publications

(26 citation statements)

References 30 publications

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“…Bailey et al use clustering and multivariate linear regression towards a similar goal [7]. These works are an excellent demonstration of the benefits of online performance and power prediction.…”

Section: Related Workmentioning

confidence: 96%

GPGPU performance and power estimation using machine learning

Greathouse

Lyashevsky

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

170

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Graphics Processing Units (GPUs) have numerous configuration and design options, including core frequency, number of parallel compute units (CUs), and available memory bandwidth. At many stages of the design process, it is important to estimate how application performance and power are impacted by these options. This paper describes a GPU performance and power estimation model that uses machine learning techniques on measurements from real GPU hardware. The model is trained on a collection of applications that are run at numerous different hardware configurations. From the measured performance and power data, the model learns how applications scale as the GPU's configuration is changed. Hardware performance counter values are then gathered when running a new application on a single GPU configuration. These dynamic counter values are fed into a neural network that predicts which scaling curve from the training data best represents this kernel. This scaling curve is then used to estimate the performance and power of the new application at different GPU configurations.Over an 8× range of the number of CUs, a 3.3× range of core frequencies, and a 2.9× range of memory bandwidth, our model's performance and power estimates are accurate to within 15% and 10% of real hardware, respectively. This is comparable to the accuracy of cycle-level simulators. However, after an initial training phase, our model runs as fast as, or faster than the program running natively on real hardware.

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Section: Related Workmentioning

confidence: 96%

GPGPU performance and power estimation using machine learning

Greathouse

Lyashevsky

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

170

View full text Add to dashboard Cite

show abstract

“…Applying ML for system design has a twofold meaning: 1 the reduction of burdens on human experts designing systems manually, and 2 the close of the positive feedback loop, i.e., architecture/system for ML and simultaneously ML for architecture/system, encouraging improvements on both sides. These applications include predictive performance modeling [18,35,44,45,52,56,90], efficient design space exploration [36,38,49,92], cache replacement [5,70,80], prefetcher [8,28,93], branch prediction [25,37], NoC design [21,63,85], power and resource management [4,31], task allocation [51,94], malware detection [15,59], compiler design [53,76], and so on.…”

Section: Related Workmentioning

confidence: 99%

Core Placement Optimization for Multi-chip Many-core Neural Network Systems with Reinforcement Learning

Deng

et al. 2020

ACM Trans. Des. Autom. Electron. Syst.

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Multi-chip many-core neural network systems are capable of providing high parallelism benefited from decentralized execution, and they can be scaled to very large systems with reasonable fabrication costs. As multi-chip many-core systems scale up, communication latency related effects will take a more important portion in the system performance. While previous work mainly focuses on the core placement within a single chip, there are two principal issues still unresolved: the communication-related problems caused by the non-uniform, hierarchical on/off-chip communication capability in multi-chip systems, and the scalability of these heuristic-based approaches in a factorially growing search space. To this end, we propose a reinforcement-learning-based method to automatically optimize core placement through deep deterministic policy gradient, taking into account information of the environment by performing a series of trials (i.e., placements) and using convolutional neural networks to extract spatial features of different placements. Experimental results indicate that compared with a naive sequential placement, the proposed method achieves 1.99× increase in throughput and 50.5% reduction in latency; compared with the simulated annealing, an effective technique to approximate the global optima in an extremely large search space, our method improves the throughput by 1.22× and reduces the latency by 18.6%. We further demonstrate that our proposed method is capable to find optimal placements taking advantages of different communication properties caused by different system configurations, and work in a topology-agnostic manner. CCS Concepts: • Computer systems organization → Architectures; Parallel architectures; • Computing methodologies → Reinforcement learning;

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“…In [11], authors present a predictive model to estimate power consumption and computation performances (i.e., execution time). The prediction is made for a given device.…”

Section: Related Work On Application Leveragesmentioning

confidence: 99%

Automatic Energy Efficient HPC Programming: A Case Study

Raïs

Coullon

Lefèvre

et al. 2018

2018 IEEE Intl Conf on Parallel &Amp; Distributed Processing With Applications, Ubiquitous Computing &Amp; Communications, Big

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Energy consumption is one of the major challenges of modern datacenters and supercomputers. By applying Green Programming techniques, developers have to iteratively implement and test new versions of their software, thus evaluating the impact of each code version on their energy, power and performance objectives. This approach is manual and can be long, challenging and complicated, especially for High Performance Computing applications. In this paper, we formally introduces the definition of the Code Version Variability (CVV) leverage and present a first approach to automate Green Programming (i.e., CVV usage) by studying the specific use-case of an HPC stencil-based numerical code, used in production. This approach is based on the automatic generation of code versions thanks to a Domain Specific Language (DSL), and on the automatic choice of code version through a set of actors. Moreover, a real case study is introduced and evaluated though a set of benchmarks to show that several trade-offs are introduced by CVV 1. Finally, different kinds of production scenarios are evaluated through simulation to illustrate possible benefits of applying various actors on top of the CVV automation.

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Adaptive Configuration Selection for Power-Constrained Heterogeneous Systems

Cited by 43 publications

References 30 publications

GPGPU performance and power estimation using machine learning

GPGPU performance and power estimation using machine learning

Core Placement Optimization for Multi-chip Many-core Neural Network Systems with Reinforcement Learning

Automatic Energy Efficient HPC Programming: A Case Study

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