Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors

Ding, Yang; Kandemir, Mahmut; Irwin, M.J.; Raghavan, Padma

doi:10.1007/978-3-540-92990-1_18

Cited by 7 publications

(2 citation statements)

References 25 publications

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“…An important direction, which is well beyond the scope of our current work, concerns the study of dynamic mappings within an appropriate runtime system or simulator that can both provide application and processor graph parameters based on measurements and allow determination of the trade-offs between achievable performance benefits and the costs of remapping while including all overheads. Earlier we considered thread migration at a multicore node to address core variations (Ding et al, 2009a,b) that demonstrated the need for lightweight strategies that can be applied at the smaller granularity of calculations at a node. In looking ahead to incorporating factors such as network congestion in a large-scale cluster within a dynamic mapping framework we conjecture that there may be a need for differentiated strategies, one within nodes at finer scales and another across nodes at coarser scales, that can inform each other and yet provide the right balance of benefits relative to costs.…”

Section: Discussionmentioning

confidence: 99%

An embedded sectioning scheme for multiprocessor topology-aware mapping of irregular applications

Kirmani

Park

Raghavan

2016

The International Journal of High Performance Computing Applica

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We consider the problem of mapping irregular applications to multiprocessor architectures whose interconnect topologies affect the latencies of data movement across processor nodes. The starting point for solutions to this problem concerns suitable weighted graph representations of an irregular application and a processor topology. Prior results for this problem have demonstrated that graph partitioning approaches can provide high-quality solutions. Additionally, when coordinate information is available for the weighted graph of the application, the geometric mapping schemes can also provide high-quality solutions. We develop and present a scheme that we call 'embedded sectioning' that directly computes a locality enhancing embedding of the weighted graph representation which is then mapped to the processor topology using recursive coordinate bisection. Our scheme is specifically directed at gaining high-quality mappings for highly irregular applications where the amount of communication can vary greatly. We evaluate the quality of mappings produced by embedded sectioning for mesh-based processor topologies using well-accepted measures including congestion, dilation and their product, referred to as the communication volume. For a test suite of unit-weight graphs mapped to a 32 3 32 mesh of processors, our method improves congestion by 26%, dilation by 52% and communication volume by 64% relative to the best values of these measures from nine other schemes. Additionally, we observe that these improvements increase with an increase in the skewness of communication in applications. For a test suite with a skewness of two the corresponding improvements for congestion, dilation and communication volume are 72%, 52% and 87%, respectively.

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Section: Discussionmentioning

confidence: 99%

An embedded sectioning scheme for multiprocessor topology-aware mapping of irregular applications

Kirmani

Park

Raghavan

2016

The International Journal of High Performance Computing Applica

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“…There are many reported works that address variation aware task mapping [16][17][18] that tries to take into account the communication requirements between the tasks while trying to maximize the performance. Ding et al's work [19] talks about adaptive application execution i.e assigning threads of an application to the cores of a chip multiprocessor with process variation using thread mapping schemes that can potentially exploit the existing heterogeneity in power and performance characteristics of the cores to optimize performance, energy consumption and energy-delay product. They also suggest that instead of globally clocking all the cores to the lowest frequency, if a subset of cores are reconfigured to their lowest frequency based on specific application behavior, significant reduction in energy-delay product can be obtained.…”

Section: Related Workmentioning

confidence: 99%

Task Assignment Algorithms for Multicore Platforms with Process Variations

Ananthanarayanan¹,

Sarangi²,

Balakrishnan³

2018

Journal of Low Power Electronics

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We have moved into an era where modern multicore systems must deal with several critical challenges such as increased power density and high temperatures. In addition to this, ITRS projects that heterogeneity due to manufacturing process variations would continue to rapidly increase in sub-nanometer technology nodes. Spatial heat influence or the lateral heat transfer is becoming more prevalent in manycore systems and has a significant impact on the processor power consumption. Thus it is becoming increasingly difficult to meet the application throughput requirements while adhering to the system power budget and thermal constraints. Many of the existing task mapping schemes that does not take into account the underlying variations in core frequency and leakage power consumption will result in sub-optimal solutions. In this work, we first formulate the mapping problem as an optimization problem and then present a rank-based, process variation and lateral heat transfer aware application mapping algorithm to solve it heuristically. Our extensive experimental results reveal that the proposed algorithm produces near optimal results (average 6% away from optimal) while being orders of magnitude faster (4000x faster for 225 cores).

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