AdapNoC: A fast and flexible FPGA-based NoC simulator

Kamali, Hadi Mardani; Hessabi, Shahin

doi:10.1109/fpl.2016.7577377

Cited by 18 publications

(4 citation statements)

References 26 publications

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“…This study did not analyze the bandwidth capability and the average packet delivery delay in the network achieved using these algorithms, since it required that modeling using special models [42,43,44] be carried out which is a rather time-consuming procedure and is subject for separate consideration. Indirectly, one can evaluate these parameters by how much the optimal path for the packets provides the algorithm.…”

Section: Testing Of Routing Algorithms For Circulants Of Various Typesmentioning

confidence: 99%

Development of routing algorithms in networks-on-chip based on two-dimensional optimal circulant topologies

Romanov

Lezhnev

Glukhikh

et al. 2020

Heliyon

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This work is devoted to the study of application of new topologies in the design of networks-on-chip (NoCs). It is proposed to use two-dimensional optimal circulant topologies for NoC design, and it is developed an optimized routing algorithm with the decreased memory usage. The proposed routing algorithm was compared with Table routing, Clockwise routing, and Adaptive routing algorithms, previously developed for ring circulant topologies, and specialized routing algorithm for multiplicative circulants. The results of synthesis of routers implementing proposed routing algorithms are presented. The cost of ALM and register resources for the implementation of communication subsystems in NoCs with circulant topologies is estimated.

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Section: Testing Of Routing Algorithms For Circulants Of Various Typesmentioning

confidence: 99%

Development of routing algorithms in networks-on-chip based on two-dimensional optimal circulant topologies

Romanov

Lezhnev

Glukhikh

et al. 2020

Heliyon

View full text Add to dashboard Cite

show abstract

“…Network on chip (NoC) is a paradigm which aims to solve the communication issues between the CPU units of the next generation of many core System on Chip (SoC). Some FPGA-based implementations to solve NoC problems include network switches typologies [194][195][196][197][198][199], buffer handling [200,201], router implementations [196,[202][203][204][205][206][207] and NoC simulators [208][209][210].…”

Section: Networkingmentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

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Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

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“…ARM Cortex A9, A12, A15). The existence of multiple mid to highperformance cores on the same die as FPGA improves the efficiency of HW/SW co-design [20,21,27,28] and provide greater flexibility is using FPGAs in data centers as re-configurable, yet powerful hardware accelerators [31,33].…”

Section: Introductionmentioning

confidence: 99%

Using Multi-Core HW/SW Co-design Architecture for Accelerating K-means Clustering Algorithm

Kamali

2018

Preprint

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The capability of classifying and clustering a desired set of data is an essential part of building knowledge from data. However, as the size and dimensionality of input data increases, the run-time for such clustering algorithms is expected to grow superlinearly, making it a big challenge when dealing with BigData.K-mean clustering is an essential tool for many big data applications including data mining, predictive analysis, forecasting studies, and machine learning. However, due to large size (volume) of Big-Data, and large dimensionality of its data points, even the application of a simple k-mean clustering may become extremely time and resource demanding. Specially when it is necessary to have a fast and modular dataset analysis flow.In this paper, we demonstrate that using a two-level filtering algorithm based on binary kd-tree structure is able to decrease the time of convergence in K-means algorithm for large datasets. The two-level filtering algorithm based on binary kd-tree structure evolves the SW to naturally divide the classification into smaller data sets, based on the number of available cores and size of logic available in a target FPGA. The empirical result on this two-level structure over multi-core FPGA-based architecture provides 330× speed-up compared to a conventional software-only solution.

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AdapNoC: A fast and flexible FPGA-based NoC simulator

Cited by 18 publications

References 26 publications

Development of routing algorithms in networks-on-chip based on two-dimensional optimal circulant topologies

Development of routing algorithms in networks-on-chip based on two-dimensional optimal circulant topologies

Field Programmable Gate Array Applications—A Scientometric Review

Using Multi-Core HW/SW Co-design Architecture for Accelerating K-means Clustering Algorithm

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