Active Voltage Balancing of Series Connected SiC MOSFET Submodules Using Pulsewidth Modulation

Abstract

Series connection of multiple transistors is an attractive solution to achieve higher voltage capability. However, the voltage imbalance among the series-connected devices is a critical issue caused by mismatches of device characteristics and gate signals. To prevent the failure of devices from the voltage imbalance, voltage balancing control (VBC) is required. In this work, an active VBC for series-connected silicon carbide (SiC) MOSFET submodules is proposed with a pulse width modulation (PWM) method. A submodule consists of two switches and one shunt capacitor, and the PWM method actively controls the capacitor voltages for balancing. The proposed VBC is simulated in MATLAB/Simulink and experimentally verified with six series-connected SiC MOSFET submodules at up to 150 kHz. The voltage balancing is achieved within 3.9 % of the targeted balanced voltage.

An enhanced single gate driven voltage‐balanced SiC MOSFET stack topology suitable for high‐voltage low‐power applications

“…From the results in Figure 10b, the voltage unbalancing of the stack under V in = 1.6 kV is achieved within 2%. However, complex sampling circuits such as ADCs are necessary to provide feedbacks, then the controller properly adjust Δt di for voltage balancing [7,8]. Obviously, such a complex gate loop and power loop design would greatly increase the total cost.…”

“…Since the gate loops and power loops of devices are not identical caused by the difference of device parasitic parameters and driving pulses, a natural voltage unbalancing exists [5]. Therefore, static voltage balancing resistors and dynamic voltage balancing circuit are necessary [6,7]. In the meantime, this way gives sufficient FIGURE 1 The structure of APSs for MMC flexibility for the adjustments of the driving pulse characteristics including voltage shapes and driving delays, which provides the basic for active voltage balancing methods.…”

High-Bandwidth Isolated Voltage Measurements With Very High Common Mode Rejection Ratio for WBG Power Converters

“…Representing (5) in the frequency-domain means that i CM increases linearly with frequency (capacitive impedance of C earth is inversely proportional to f ), i.e., with +20 dB/dec. In combination with the said ohmic-inductive impedance Z line of the connection between DUT and probe (indicated in Fig.…”

“…The scaling of the area-specific on-state resistance with device blocking voltage renders series connection of multiple Low-Voltage (LV) transistors attractive to achieve a certain overall blocking voltage [2]. Thereby, the knowledge of static and/or dynamic device DS voltage sharing, which due to the series connection requires floating low parasitic capacitance measurements, is very important to prevent failures due to overvoltage [5].…”