ACMA: Accuracy-configurable multiplier architecture for error-resilient System-on-Chip

Bhardwaj, Kartikeya; Mane, Pravin

doi:10.1109/recosoc.2013.6581532

Cited by 14 publications

(2 citation statements)

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“…The use of approximate multipliers in image process applications, which leads to reductions in power consumption, delay, and transistor count compared with those of an exact multiplier design, has been discussed in the literature. In [10], an accuracy-configurable multiplier architecture (ACMA) was suggested for error-resilient systems.…”

Section: Literature Surveymentioning

confidence: 99%

A Methodology for Improvement of Roba Multiplier for Electronic Applications

Daniel¹,

Deepa²

2019

VLSICS

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In this paper, propose an approximate multiplier that is high speed yet energy efficient. The approach is to around the operands to the closest exponent of 2. This way the machine intensive a part of the multiplication is omitted up speed and energy consumption. The potency of the planned multiplier factor is evaluated by comparing its performance with those of some approximate and correct multipliers using different design parameters. In this proposed approach combined the conventional RoBA multiplier with Kogge-stone parallel prefix adder. The results revealed that, in most (all) cases, the newly designed RoBA multiplier architectures outperformed the corresponding approximate (exact) multipliers. Thus improved the parameters of RoBA multiplier which can be used in the voice or image smoothing applications in the DSP.

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Section: Literature Surveymentioning

confidence: 99%

A Methodology for Improvement of Roba Multiplier for Electronic Applications

Daniel¹,

Deepa²

2019

VLSICS

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“…In [5], the authors present an under-designed multiplier achieving up to 45 % energy savings. This complexity reduction served as a basis to create inexact arithmetic circuits such as adders [4], [6] and multipliers [7]. However, these computational blocks have been tested empirically, and all present different amounts of errors.…”

Section: Introductionmentioning

confidence: 99%

Automatic generation of inexact digital circuits by gate-level pruning

Schlachter

Camus

Enz

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-Inexact or approximate circuits show great ability to reduce power consumption at the cost of occasional errors in comparison to their conventional counterparts. Even though the benefits of such circuits have been proven for many applications, they are not wide spread owing to the absence of a clear design methodology and the required CAD tools. In this regard, this paper presents a methodology to automatically generate inexact circuits starting from a conventional design by adding only one small step in the digital design flow. Further, this paper also demonstrates that achieving pruning at gate-level can lead to substantial savings in terms of power consumption, critical path delay and silicon area. An order of magnitude area and power savings is demonstrated for a 64-bit gate-level pruned high-speed adder for a 10 % relative error magnitude.

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