Achieving uniform performance and maximizing throughput in the presence of heterogeneity

Rangan, K.K.; Powell, Michael D.; Wei, Gu-Yeon; Brooks, David

doi:10.1109/hpca.2011.5749712

Cited by 28 publications

(15 citation statements)

References 24 publications

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“…Prior research on AMPs has shown the need for having the right set of core types that can improve the performance and lower the energy of both single-threaded and multi-threaded applications [1], [6], [17], [18]. Kumar et al proposed having a right mix of heterogeneous cores such that each program phase of an application is mapped to a core that achieves the largest power reduction and performance improvement [1].…”

Section: A Asymmetric Multicore Processors (Amps)mentioning

confidence: 99%

Online mechanism for reliability and power-efficiency management of a dynamically reconfigurable core

Srinivasan

Koren

Kundu

2015

2015 33rd IEEE International Conference on Computer Design (ICCD)

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Previous studies have shown that the best way to achieve high throughput/Watt of a single threaded application is by running it on an asymmetric multicore processor (AMP). AMPs feature cores that are tuned for specific workload characteristics. To increase efficiency, the core that offers the best power-performance trade-off for the executing thread is chosen. To reduce the overhead of thread migration, we have previously proposed a morphable core that can morph into multiple core types. In this study, apart from power-performance efficiency, we also consider the reliability of the different core types as indicated by their vulnerability to soft-errors. We show that the best core type for power-efficiency may not be the best for reliability. Accordingly, we develop a multi-objective thread migration strategy to determine the best core type considering power efficiency and reliability. To support runtime decision making, we have developed online estimators for reliability and power efficiency based on performance monitoring counters. In keeping with the existing literature, we use the architectural vulnerability factor (AVF) as the metric for reliability and instructions-per-second 2 /Watt as the metric for power efficiency. For the multi-objective optimization we use a Cobb-Douglas production function. Our results indicate that the proposed runtime mechanism for reliability and power-efficiency improves, on the average, the throughput/Watt of applications by 24% and reduces the Soft-Error Rate (SER) by 12% compared to the best static execution.

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Section: A Asymmetric Multicore Processors (Amps)mentioning

confidence: 99%

Online mechanism for reliability and power-efficiency management of a dynamically reconfigurable core

Srinivasan

Koren

Kundu

2015

2015 33rd IEEE International Conference on Computer Design (ICCD)

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“…It allows good control state management by offering great control granularity with features such as excellent noise isolation using simple mathematics. Drawbacks in this approach include thread starvation 3 and data poverty 4 especially in high mix environments where metrology sampling is used. The initialization of expired control threads using pilot lots or running full production lots with less accurate recipe settings are both costly results of thread starvation.…”

Section: Introductionmentioning

confidence: 99%

Lithography run-to-run control in high mix manufacturing environment with a dynamic state estimation approach

Yelverton¹,

Agrawal²

2014

Metrology, Inspection, and Process Control for Microlithography XXVIII

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The quest to create robust control solutions for Photolithography processes is an ongoing matter. Over the past few decades several threaded and non-threaded Run-to-Run (RtR) control solutions have been introduced addressing various specific Lithography process control requirements. With continually shrinking semiconductor technology nodes, greater interdependencies are being observed between processes requiring more complex control solutions that rely on increasing process context. With higher product mixes, associated metrology costs add to this growing complexity in using existing control solutions effectively.A new dynamic RtR control solution approach in GLOBALFOUNDRIES high mix manufacturing environment offering coverage to all Lithography process steps in Fab8 has been architected and implemented. This approach not only addresses the issues caused in most commonly used 'Threaded' and 'Non-Threaded' control approaches in Lithography but also offers a dynamic thread definition implementation approach.

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“…Power variation usually changes as processors age, thus requiring continuing characterization during their lifetimes [2]. Rangan et al [16] observe that variation across cores can be evidenced by variation in the highest frequency that each core can support. Rather than using the minimum frequency across all cores, they recommend classifying the processor using the average core frequency, thus effectively masking core heterogeneity.…”

Section: Related Workmentioning

confidence: 99%

Beyond DVFS: A First Look at Performance under a Hardware-Enforced Power Bound

Rountree

Ahn

Supinski

et al. 2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &Amp; PhD Forum

145

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Abstract-Dynamic Voltage Frequency Scaling (DVFS) has been the tool of choice for balancing power and performance in high-performance computing (HPC). With the introduction of Intel's Sandy Bridge family of processors, researchers now have a far more attractive option: user-specified, dynamic, hardware-enforced processor power bounds. In this paper we provide a first look at this technology in the HPC environment and detail both the opportunities and potential pitfalls of using this technique to control processor power.As part of this evaluation we measure power and performance for single-processor instances of several of the NAS Parallel Benchmarks. Additionally, we focus on the behavior of a single benchmark, MG, under several different power bounds. We quantify the well-known manufacturing variation in processor power efficiency and show that, in the absence of a power bound, this variation has no correlation to performance. We then show that execution under a power bound translates this variation in efficiency into variation in performance.

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Achieving uniform performance and maximizing throughput in the presence of heterogeneity

Cited by 28 publications

References 24 publications

Online mechanism for reliability and power-efficiency management of a dynamically reconfigurable core

Online mechanism for reliability and power-efficiency management of a dynamically reconfigurable core

Lithography run-to-run control in high mix manufacturing environment with a dynamic state estimation approach

Beyond DVFS: A First Look at Performance under a Hardware-Enforced Power Bound

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