Achieving uniform nMOS device power distribution for sub-micron ESD reliability

Duvvury,; Díaz,; Haddock,

doi:10.1109/iedm.1992.307325

Cited by 66 publications

(18 citation statements)

References 5 publications

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“…OR multifinger nMOS protection, it has been recognized that the gate coupling technique is efficient since it ensures uniform triggering of the lateral n-p-n bipolar transistors [1], [2]. However, its effectiveness is dubious in silicided processes [3].…”

mentioning

confidence: 99%

Analysis of gate-bias-induced heating effects in deep-submicron ESD protection designs

Oh¹,

Duvvury

Banerjee

et al. 2002

IEEE Trans. Device Mater. Relib.

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Abstract-This paper presents a detailed investigation of the degradation of electrostatic discharge (ESD) strength with high gate bias for deep-submicron salicided ESD protection nMOS transistors, which has significant implications for protection designs where high gate coupling occurs under ESD stress. It has been shown that gate-bias-induced heating is the primary cause of early ESD failure and that this impact of gate bias depends on the finger width of the protection devices. In addition, it has been established that substrate biasing can effectively alleviate the adverse impact of the gate bias and can improve ESD strength despite the gate-coupling level. Improved understanding of ESD behavior for advanced devices under high gate-coupling conditions can extend design capabilities of protection structures.Index Terms-Electrostatic discharges, ESD protection, gate-bias-induced heating, salicided nMOS transistor, second breakdown triggering current.

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mentioning

confidence: 99%

Analysis of gate-bias-induced heating effects in deep-submicron ESD protection designs

Oh¹,

Duvvury

Banerjee

et al. 2002

IEEE Trans. Device Mater. Relib.

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“…But, during ESD stress, the multiple fingers of ESD protection NMOS cannot be uniformly turned on. Only several fingers of the NMOS were turned on and therefore damaged by ESD [4]. The EMMI photography on the turn-on behavior of a gate-grounded NMOS (W/L= 300µm/0.35µm) under a 40mA drain pulse current stress is shown in Fig.5.…”

Section: Substrate-triggered Techniquementioning

confidence: 99%

“…To improve the turn-on uniformity among the multiple fingers, the gate-driven design [4]- [6] and substrate-triggered design [7]- [11] had been reported to increase ESD level of the large-device-dimension NMOS. The circuit schematic diagrams are shown in Fig.…”

Section: Fig5mentioning

confidence: 99%

Whole-chip ESD protection strategy for CMOS integrated circuits in nanotechnology

Ker

Jiang

Proceedings of the 2001 1st IEEE Conference on Nanotechnology. IEEE-NANO 2001 (Cat. No.01EX516)

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On-chip electrostatic discharge (ESD) protection circuits had been built in IC chips to protect the devices and circuits against ESD damage. But, ESD protection circuits constructed with the scaled-down CMOS devices are very weak to ESD stress. Therefore, novel ESD protection solutions must be developed to overcome this reliability challenge for integrated circuits fabricated in the nano-scale CMOS technology. In this paper, the whole-chip ESD protection strategy for CMOS integrated circuits in nanotechnology has been proposed with two main methods. One is the substrate-triggered circuit technique used to effectively improve ESD robustness of devices in the nano-scale CMOS technology. The other is the novel design concept of "ESD Buses" used to solve the internal ESD damage issue of CMOS IC with multiple and separated power lines. The internal circuits or interface circuits, realized by nano-scale CMOS devices, are more sensitive to such internal ESD damage issue. By using ESD buses, ESD current can be quickly discharged far away from the internal circuits or interface circuits of CMOS IC to achieve the goal of whole-chip ESD protection.

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“…Non-uniform turn-on phenomenon can be alleviated by increasing the ballast resistance to increase Vt2, or by gate-driven technique to lower Vt1 [4]- [6]. The traditional gate-coupled technique with simple RC circuit is shown in Fig.…”

Section: Over-date-driven Effectmentioning

confidence: 99%

“…However, due to the nonuniform turn-on effect, ESD robustness of NMOS with multi-finger layout style was not linearly increased when the device dimension of NMOS is increased. To improve turn-on uniformity among the multi-fingers of ESD protection NMOS, the gate-driven (or gate-coupled) technique had been reported to increase ESD level of the large-device-dimension NMOS [4]- [6]. By using the gate-driven design, some ESD transient voltage is coupled to the gate of ESD protection NMOS during ESD transition to enhance turn-on uniformity among its multiple fingers.…”

Section: Introductionmentioning

confidence: 99%

Design to avoid the over-gate-driven effect on ESD protection circuits in deep-submicron CMOS processes

Ker

Chen

SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720)

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Achieving uniform nMOS device power distribution for sub-micron ESD reliability

Cited by 66 publications

References 5 publications

Analysis of gate-bias-induced heating effects in deep-submicron ESD protection designs

Analysis of gate-bias-induced heating effects in deep-submicron ESD protection designs

Whole-chip ESD protection strategy for CMOS integrated circuits in nanotechnology

Design to avoid the over-gate-driven effect on ESD protection circuits in deep-submicron CMOS processes

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