Accurate SPICE compatible CNT interconnect and CNTFET models for circuit design and simulation

Yamaçli, Serhan; Avcı, Mutlu

doi:10.1016/j.mcm.2012.11.014

Cited by 12 publications

(5 citation statements)

References 23 publications

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“…Among these procedures, DFT simulations provide proven results thanks to the fact that Schrodinger’s equation is solved numerically with exchange-correlation functionals which model the electron–electron and electron–ion interactions accurately. DFT is a widely-used method in ab initio simulations giving precise results for a broad range of nano devices such as CNTs [ 45 ], graphene [ 46 ] and molecular devices [ 47 ]. Various parameters such as electron density, DOS and total energy of nano structures can be obtained utilizing DFT.…”

Section: Methodsmentioning

confidence: 99%

Voltage-Dependent Electronic Transport Properties of Reduced Graphene Oxide with Various Coverage Ratios

Yamaçli

2014

Nano-Micro Lett.

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Graphene is mainly implemented by these methods: exfoliating, unzipping of carbon nanotubes, chemical vapour deposition, epitaxial growth and the reduction of graphene oxide. The latter option has the advantage of low cost and precision. However, reduced graphene oxide (rGO) contains hydrogen and/or oxygen atoms hence the structure and properties of the rGO and intrinsic graphene are different. Considering the advantages of the implementation and utilization of rGO, voltage-dependent electronic transport properties of several rGO samples with various coverage ratios are investigated in this work. Ab initio simulations based on density functional theory combined with non-equilibrium Green’s function formalism are used to obtain the current–voltage characteristics and the voltage-dependent transmission spectra of rGO samples. It is shown that the transport properties of rGO are strongly dependent on the coverage ratio. Obtained results indicate that some of the rGO samples have negative differential resistance characteristics while normally insulating rGO can behave as conducting beyond a certain threshold voltage. The reasons of the peculiar electronic transport behaviour of rGO samples are further investigated, taking the transmission eigenstates and their localization degree into consideration. The findings of this study are expected to be helpful for engineering the characteristics of rGO structures.

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Section: Methodsmentioning

confidence: 99%

Voltage-Dependent Electronic Transport Properties of Reduced Graphene Oxide with Various Coverage Ratios

Yamaçli

2014

Nano-Micro Lett.

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“…Various carbon nanotube FET (CNTFET) models have been reported in recent years [15][16][17][18][19][20][21][22]; however, some of them use simplifications, making it questionable when evaluating the transient response and device dynamic performance, while other models are described in terms of an integral function that requires intensive calculation efforts, making it difficult to implement in circuit simulators like SPICE. Recently, two very effective models for CNT have been developed at Stanford [5,6,9,10]: (i) a circuit-compatible SPICE model for CNTFET, (ii) a compact virtual source model for CNTFET.…”

Section: Formulation Of the Compact Cntfet Modelmentioning

confidence: 99%

A Compact and Robust Technique for the Modeling and Parameter Extraction of Carbon Nanotube Field Effect Transistors

et al. 2020

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Carbon nanotubes field-effect transistors (CNTFETs) have been recently studied with great interest due to the intriguing properties of the material that, in turn, lead to remarkable properties of the charge transport of the device channel. Downstream of the full-wave simulations, the construction of equivalent device models becomes the basic step for the advanced design of high-performance CNTFET-based nanoelectronics circuits and systems. In this contribution, we introduce a strategy for deriving a compact model for a CNTFET that is based on the full-wave simulation of the 3D geometry by using the finite element method, followed by the derivation of a compact circuit model and extraction of equivalent parameters. We show examples of CNTFET simulations and extract from them the fitting parameters of the model. The aim is to achieve a fully functional description in Verilog-A language and create a model library for the SPICE-like simulator environment, in order to be used by IC designers.

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“…The SNM is defined as the maximum amount of voltage noise that can be tolerated at the cross -inverter output nodes without flipping the cell [25]. It could be determined by the voltage transfer characteristics (VTCs) of the cross -coupled inverters.…”

Section: B Sram Cellsmentioning

confidence: 99%

Channel and Gate Workfunction-Engineered CNTFETs for Low-Power and High-Speed Logic and Memory Applications

Wang¹,

Xu²,

Huang³

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short -channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self -consistently with Poisson's equations. It is revealed that heteromaterial -gate and lightly doped drain and source CNTFET (HMG -LDDS -CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look -up table(LUT) based Verilog -A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of Ф M1 /Ф M2 have been concluded in terms of power consumption, average delay, stability, energy consumption and power -delay product (PDP). In addition, we discuss and compare the CNTFETbased circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS -HMG -CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

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Accurate SPICE compatible CNT interconnect and CNTFET models for circuit design and simulation

Cited by 12 publications

References 23 publications

Voltage-Dependent Electronic Transport Properties of Reduced Graphene Oxide with Various Coverage Ratios

Voltage-Dependent Electronic Transport Properties of Reduced Graphene Oxide with Various Coverage Ratios

A Compact and Robust Technique for the Modeling and Parameter Extraction of Carbon Nanotube Field Effect Transistors

Channel and Gate Workfunction-Engineered CNTFETs for Low-Power and High-Speed Logic and Memory Applications

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