Accurate SI filters using RGC integrators

Goldenberg, M.; Croman, R.; Fiez, T.S.

doi:10.1109/4.328641

Cited by 29 publications

(3 citation statements)

References 12 publications

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“…where is the modulation index and has been assumed − as it occurs in most practical cases. Note that, as and are proportional to , they can be reduced by using the same strategies to attenuate : either by increasing [20] or by reducing [21].…”

Section: A Finite Output-input Conductance Ratio Errormentioning

confidence: 99%

Analysis of Error Mechanisms in Switched-Current Sigma-Delta Modulators

Rosa

Pérez-Verdú

Medeiro

et al. 2004

Analog Integrated Circuits and Signal Processing

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This paper presents a systematic analysis of the major switched-current (SI) errors and their influence on the performance degradation of Σ∆ Modulators (Σ∆Ms). The study is presented in a hierarchical systematic way. First, the physical mechanisms behind SI errors are explained and a precise modeling of the memory cell is derived. Based on this modeling, the analysis is extended to other circuits of higher level in the modulator hierarchy such as integrators and resonators. After that, the study is extended to the modulator level, considering two fundamental architectures: a 2nd-order LowPass Σ∆M (2nd-LPΣ∆M) and a 4th-order BandPass Σ∆M (4th-BPΣ∆M). The noise shaping degradation caused by the linear part of SI errors is studied in the first part of the paper. This study classifies SI non-idealities in different categories

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Section: A Finite Output-input Conductance Ratio Errormentioning

confidence: 99%

Analysis of Error Mechanisms in Switched-Current Sigma-Delta Modulators

Rosa

Pérez-Verdú

Medeiro

et al. 2004

Analog Integrated Circuits and Signal Processing

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“…The SI integrator circuit shown in Fig. 4 is taken for the experiment and its ideal transfer function can be expressed as follows: (10) Applying the simple CSH model, the SI integrators, including first generation, second generation, dynamic, cascode, folded cascode structure, and others [18], [19], [20], all can be simplified as the model shown in Fig. 5 where the nonideal effects have been taken into account.…”

Section: Efficient System Analysis Basedmentioning

confidence: 99%

Offset current cancellation based on a multiple-path feedback compensation (MPFC) technique for switched-current circuits and systems

Kuo

Lee

Chen

1997

IEEE Trans. Circuits Syst. II

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This paper presents a new offset current cancellation technique called multiple-path feedback compensation (MPFC) for greatly reducing offset currents at both output and internal nodes of SI circuits and systems. In order to analyze the effects and the statistical distribution of dc current offsets of large SI systems, a very simple and efficient SI model is first used. This model can be used for fast, accurate, statistical, and systematic analyzes of system characteristics such as offset current, frequency response, stability, scaling, and sensitivity. Based on the model, a complex SI system can be transferred to a simple signal flow graph, which can be represented by linear state equations. From the state equations, statistical Monte Carlo simulation is used to obtain optimal MPFC coefficients. A fifth-order Chebyshev SI filter is illustrated as an example for implementation and verification of the proposed MPFC technique. Ninety test chips have been fabricated with a 1-m CMOS n-well digital process.Increased percentages of circuit area and power consumption due to the use of the MPFC circuit are 5% and 4%, respectively. Measured results show that the variance of output offset currents is reduced to 2% of its original amount. Besides, the peak signalto-noise ratio (PSNR) is increased by 3 dB and the total harmonic distortion is reduced by 10 dB.

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“…For discrete-time circuits, this technique is a promising alternative to the switched-capacitor technique. A number of designs including filters, converters, delay lines, modulators and other functional blocks have been reported [1][2][3][4][5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

Functional and structural testing of switched-current circuits

Renovell

Azaïs

Bodin

et al.

European Test Workshop 1999 (Cat. No.PR00390)

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This paper aims at defining an efficient test strategy for switched-current circuit testing. Taking into account the specificity of these circuits, we propose an original structural test technique as an alternative to traditionallyused functional verification. This technique is validated both at the cell and block levels. Test results demonstrate that a high fault coverage can be achieved with a low cost test procedure. A mixed strategy combining benefits of functional and structural approaches is derived

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Accurate SI filters using RGC integrators

Cited by 29 publications

References 12 publications

Analysis of Error Mechanisms in Switched-Current Sigma-Delta Modulators

Analysis of Error Mechanisms in Switched-Current Sigma-Delta Modulators

Offset current cancellation based on a multiple-path feedback compensation (MPFC) technique for switched-current circuits and systems

Functional and structural testing of switched-current circuits

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