Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices

Krishnaswamy, Smita; Viamontes, George F.; Markov, Igor L.; Hayes, John P.

doi:10.1109/date.2005.47

Cited by 225 publications

(141 citation statements)

References 12 publications

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“…Compared to this improved matrix method, our BP method still shows significant advantage. For example: the circuit 9symm1 (9 inputs, 1 outputs, 44 gates) in [3] has comparable size and complexity with the 4-bit adders in our simulations. It took 1758 seconds and 1200MB to compute SER of this circuit in [3].…”

Section: Simulations and Comparisons Withmentioning

confidence: 98%

“…For example: the circuit 9symm1 (9 inputs, 1 outputs, 44 gates) in [3] has comparable size and complexity with the 4-bit adders in our simulations. It took 1758 seconds and 1200MB to compute SER of this circuit in [3]. Another example is circuit pm1 (27 inputs, 17 outputs, 24 gates), which took 7169 seconds and 160MB to calculate its SER in [3].…”

Section: Simulations and Comparisons Withmentioning

confidence: 98%

“…For an 8-bit CSA, the matrix size exceeds 1TB, which is beyond the capability of current computers. The matrix model was improved in [3] to handle larger circuits more efficiently. Compared to this improved matrix method, our BP method still shows significant advantage.…”

Section: Simulations and Comparisons Withmentioning

confidence: 99%

“…However, both CPU time and memory requirements grow exponentially as the number of inputs and outputs increases. In [3], algebraic decision diagrams were employed to improve the efficiency of the matrix model, but the memory requirements are huge for complicated circuits. In this paper, we propose a new methodology to evaluate error distribution within circuits based on belief propagation.…”

Section: Introductionmentioning

confidence: 99%

“…In nanoscale devices and circuits, two types of errors are unavoidable, i.e., hardware faults and signal faults [2], [3]. In order to make nanoscale systems reliable, the design of fault-tolerant architectures is necessary.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation

Rao

Chen

Zhao

et al. 2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-As silicon circuits quickly approach their physical limitations, researchers are actively looking for novel building blocks to develop nanocircuits. However, future nanoelectronic circuits are more error-prone than conventional CMOS designs because of their self-assembly design. To help design fault-tolerant nanoscale circuits, new circuit design and testing tools are needed. In this paper, an efficient methodology to evaluate nanoscale circuit fault tolerance based on Belief Propagation (BP) algorithm is proposed. Compared with existing approaches, the BP algorithm is more efficient in terms of memory requirements and CPU times. The proposed methodology can be easily run on multiple CPUs to achieve parallel processing and thus further reduces simulation time.

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Section: Simulations and Comparisons Withmentioning

confidence: 98%