Accurate estimation of defect-related yield loss in reconfigurable VLSI circuits

Khare, J.; Feltham, D.B.I.; Maly, W.

doi:10.1109/4.192046

Cited by 42 publications

(10 citation statements)

References 21 publications

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“…Using simulation approaches with prototype CAD tools, Khare et al [9] show that the critical area for these fatal flaws, plotted against the defect radius, may be either very high (100 m or above) for all realistic defect radii or nonexistent for all realistic defect radii, depending on which of two possible RAM layout templates are chosen. BISRAMGEN implements the 6T SRAM cell layout that causes a near-zero critical area for these fatal faults.…”

Section: Yield Improvementmentioning

confidence: 99%

“…In this model, we may lump together all the macrocells that are assumed to include no redundancy or self-repair, as done by Khare et al [9], and analyze the yield of only the RAM. This approach, however, is complicated by two factors, namely: a) defects in the RAM layout may have global effects on the chip and b) if the chip area is limited, the effective area within the chip (i.e., the area available for placement and routing of the other macrocells) is reduced as a consequence of BISR in its caches, and this may impose layout constraints on the other macrocells.…”

Section: Yield Improvementmentioning

confidence: 99%

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A physical design tool for built-in self-repairable RAMs

Chakraborty

Kulkami

Bhattacharya

et al. 2001

IEEE Trans. VLSI Syst.

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Abstract-In this paper, we present the description and evaluation of a novel physical design tool, BISRAMGEN, that can generate reconfigurable and fault-tolerant RAM modules. This tool, first proposed in [3], designs a redundant RAM array with accompanying built-in self-test (BIST) and built-in self-repair (BISR) logic that can switch out faulty rows and switch in spare rows. Built-in self-repair causes significant improvement in reliability, production yield, and manufacturing cost of ASICs and microprocessors with embedded RAMs.

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Section: Yield Improvementmentioning

confidence: 99%

Section: Yield Improvementmentioning

confidence: 99%

A physical design tool for built-in self-repairable RAMs

Chakraborty

Kulkami

Bhattacharya

et al. 2001

IEEE Trans. VLSI Syst.

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“…Proceedings of the 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'02) 1063-6722/02 $17.00 © 2002 IEEE As a result, the chip yield, Y Total , is given by [1] ( ) α…”

Section: Repair Yield Calculationmentioning

confidence: 99%

“…Researchers have studied repair yield simulation because it is needed for redundancy optimization in chip design. Khare et al predicted the repair yield by extracting repairable and un-repairable nodes from the circuit layout [1]. Ciplickas et al estimated the repair yield by calculating yield-loss events caused by various failed node combinations [2] [3].…”

Section: Introductionmentioning

confidence: 99%

Repair yield simulation with iterative critical area analysis for different types of failure

Hamamura

Nemoto²,

Kumazawa³

et al.

17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.

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We propose a general method for repair-yield estimation based on critical area analysis using a commercial Monte-Carlo simulator. We classify failures into several types according to the repair rules and use iterative critical area analysis for each type of failure (ICAA-ETF) to calculate the repair yield. Our proposed method makes it possible to accurately estimate within a few hours the repair yield of a memory product. An example of application to an actual SRAM product is discussed to illustrate in detail how our method can be used for critical area calculation and repair-yield modeling.

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“…We propose such an algorithm. This algorithm has been implemented in SENSAT together with a known algorithm [3] which determines the sensitive areas for shorts. A practical example of optimization of an analog CMOS cell layout shows how our tool can be used to reduce the sensitivity of a layout to spot defects.…”

mentioning

confidence: 99%

SENSAT-a practical tool for estimation of the IC layout sensitivity to spot defects

Pleskacz¹,

Kuzmicz²

Proceedings the European Design and Test Conference. ED&TC 1995

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Shorts and opens caused by spot defects may result in significant yield loss in manufacturing of VLSI circuits. Traditionally a layout design is considered correct and manufacturable if it does not contain any violations of the geometric design rules. However, it is well known that two different layouts of the same integrated circuit may exhibit different sensitivities to spot defects despite the fact that both are free from design rule violations and both occupy the same area. Therefore, a tool for verification of sensitivity to spot defects and estimation of spot defect related yield losses would be very helpful in optimization of an IC design from the viewpoint of manufacturability.This work starts from the discussion of the relationship between occurrence of a spot defect and the circuit failure. Since a bridge between two separate conducting regions is not equivalent to a short in the circuit, and a break in a conducting layer is not equivalent to an open connection, no geometrical analysis of a single mask can provide exact estimation of the mask sensitivity to spot defect related shorts and opens. In the general case such an estimation requires understanding of the operation of the circuit. We introduce the concept of the sensitive area defined as the area containing the centers of all defects of a given radius R which result in bridges (or breaks). The sensitive area is not identical with the critical area. The critical area, as defined by others [1,2], is the area containing the centers of all defects of a given radius R which result in malfunction of the circuit. We say that a region in an IC mask is sensitive but not critical if defects with centers located in this region create bridges or breaks which do not affect operation of the circuit. It is possible to extract from a single mask its sensitive area but not its critical area. If the sensitive area is extracted and displayed, the designer may ignore some parts of it if he or she knows that they are not critical. As a result, a practical tool for IC layout optimization which is based on the concept of sensitive area must be interactive. SENSAT is such a tool.Since reduction of the layout sensitivity to shorts may increase its sensitivity to opens and vice versa, a practical tool must determine sensitive areas for both. The main function of SENSAT is to extract and display the sensitive areas in the IC masks. Crucial algorithms in SENSAT are the algorithms which determine shapes of the sensitive areas for shorts and opens in the actual layout. In this work we focus our attention on the sensitive area for opens. We demonstrate that in the case of arbitrary mask geometry there are qualitative differences between the concepts of the sensitive areas for shorts and for opens, and a more complex algorithm is needed to find the sensitive areas for opens. We propose such an algorithm. This algorithm has been implemented in SENSAT together with a known algorithm [3] which determines the sensitive areas for shorts. A practical example of optimization of an an...

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Accurate estimation of defect-related yield loss in reconfigurable VLSI circuits

Cited by 42 publications

References 21 publications

A physical design tool for built-in self-repairable RAMs

A physical design tool for built-in self-repairable RAMs

Repair yield simulation with iterative critical area analysis for different types of failure

SENSAT-a practical tool for estimation of the IC layout sensitivity to spot defects

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