Accurate estimation of analog test metrics with extreme circuits

Beznia, Kamel; Bounceur, Ahcène; Abdallah, L.; Huang, Ke; Mir, Salvador; Euler, Reinhardt

doi:10.1109/icecs.2012.6463748

Cited by 3 publications

(4 citation statements)

References 6 publications

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“…This model is next used for the selection of Monte Carlo circuit instances that, when electrically simulated, will likely produce extreme values in the output parameter space. By using this technique, known as statistical blockade [Singhee and Rutenbar 2009], it is possible to generate a population of extreme devices for a more accurate estimation of test metrics [Stratigopoulos and Mir 2010;Beznia et al 2012], provided that the input parameter space model is accurate enough. These techniques are obviously harder to apply than those of the first phase since they also require a model of the input parameter space.…”

Section: Methodological Flow For Model Selectionmentioning

confidence: 99%

“…We will describe next one technique for the estimation of test metrics using extreme values [Beznia et al 2012]. This corresponds to the second phase of the methodological flow in Figure 1 and considers the set of circuits that pass the test to estimate T E , and the set of circuits that are functional to estimate Y L .…”

Section: The Multivariate Extreme Value Modelmentioning

confidence: 99%

“…(34). In Beznia et al [2012], we have shown the estimation of test metrics for the evaluation of an RF LNA BIST technique using this extreme value model. The precision obtained using 40 · 10 4 circuits generated with this algorithm is the same as that obtained with the direct estimation over the reference set of 1 million circuits.…”

Section: The Multivariate Extreme Value Modelmentioning

confidence: 99%

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A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters

Beznia

Bounceur

Euler

et al. 2015

ACM Trans. Des. Autom. Electron. Syst.

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Testing analog integrated circuits is expensive in terms of both test equipment and time. To reduce the cost, Design-For-Test techniques (DFT) such as Built-In Self-Test (BIST) have been developed. For a given Circuit Under Test (CUT), the choice of a suitable technique should be made at the design stage as a result of the analysis of test metrics such as test escapes and yield loss. However, it is very hard to carry out this estimation for analog/RF circuits by using fault simulation techniques. Instead, the estimation of parametric test metrics is made possible by Monte Carlo circuit-level simulations and the construction of statistical models. These models represent the output parameter space of the CUT in which the test metrics are defined. In addition, models of the input parameter space may be required to accelerate the simulations and obtain higher confidence in the DFT choices. In this work, we describe a methodological flow for the selection of most adequate statistical models and several techniques that can be used for obtaining these models. Some of these techniques have been integrated into a Computer-Aided Test (CAT) tool for the automation of the process of test metrics estimation. This estimation is illustrated for the case of a BIST solution for CMOS imager pixels that requires the use of advanced statistical modeling techniques. . 2015. A tool for analog/RF BIST evaluation using statistical models of circuit parameters.

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Section: Methodological Flow For Model Selectionmentioning

confidence: 99%

Section: The Multivariate Extreme Value Modelmentioning

confidence: 99%

Section: The Multivariate Extreme Value Modelmentioning

confidence: 99%

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A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters

Beznia

Bounceur

Euler

et al. 2015

ACM Trans. Des. Autom. Electron. Syst.

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“…Later, a similar technique has been considered in [32] to estimate test metrics in a univariate case (a single output performance). The work [33] shows how extreme circuits can be used for an accurate computation of test metrics within a multivariate case study, assuming that the statistical learning technique proposed in [31] can be applied. However, the theory used is very complicated and not easy to apply, especially for circuits having an important number of performances and test measures.…”

Section: Prior Workmentioning

confidence: 99%

A Classification Approach for an Accurate Analog/RF BIST Evaluation Based on the Process Parameters

et al. 2018

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Specifications of Radio Frequency (RF) analog integrated circuits have increased strictly as their applications tend to be more complicated and high test cost demanding. This makes them very expensive due to an increased test time and to the use of sophisticated test equipment. Alternative test measures, extracted by means of Built-In Self Test (BIST) techniques, are useful approaches to replace standard specification-based tests. One way to evaluate the efficiency of the CUT measures at the design stage is by estimating the Test Escapes (T E) and the Yield Loss (Y L) at ppm level. Unfortunately, an important number of Monte Carlo simulations must be run in order to guarantee their accuracy. For certain types of circuits, this requires many months or even years to generate millions of circuits. To overcome this limitation, we present in this paper a new technique where a small number of simulations is sufficient to reach an important precision. This method is based on a classification using machine learning methods, such as SVM and Neural Networks based classifiers to determine pass/fail regions. The proposed approach requires a few number of simulations only to determine the region separating the process parameters generating good and faulty, or pass and fail circuits. Then only this region is needed to estimate the test metrics without running any additional simulation. The proposed methodology is illustrated for the evaluation of a filter BIST technique. Keywords Analog/RF test • SVM classification • Neural Network classification • BIST evaluation 1 Introduction The test is a very important notion in the field of the validation step of analog circuit design. It is the way to confirm whether a circuit under test (CUT) satisfies all functional specifications that represent its performance parameters. Since there are no manufactured circuits at the design stage, test errors can only be

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Accurate analog/RF BIST evaluation based on SVM classification of the process parameters

Bounceur

Brahmi

Beznia

et al. 2014

2014 9th International Design and Test Symposium (IDT)

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Accurate estimation of analog test metrics with extreme circuits

Cited by 3 publications

References 6 publications

A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters

A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters

A Classification Approach for an Accurate Analog/RF BIST Evaluation Based on the Process Parameters

Accurate analog/RF BIST evaluation based on SVM classification of the process parameters

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