Accurate and efficient simulation of synchronous digital switching noise in systems on a chip

Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry

“…For very large digital blocks, simulation of substrate noise coupling is not practical to do at the transistor level. An efficient methodology presented in [6] uses a gate-level VHDL description of the digital system to generate transition information. This information is then combined with a noise signature library for each gatelevel block to determine cell noise currents.…”

Noise Figure Degradation Analysis of Power/Ground Noise on 900MHz LNA for UHF RFID

“…The power/ground noise of LNA actually contains various frequency components because it is induced from the coupling of digital circuit switching noise or coupling of digital clock signal. [7] However, to analyze the effect of power/ground noised more fundamentally, it is modeled as a 1-tone sinusoidal voltage source. With the result, the effect of power/ground noise from digital circuit switching noise can be also analyzed by superposition of each 1-tone noise.…”

Schematic-Driven Substrate Noise Coupling Analysis in Mixed-Signal IC Designs

“…Because there is no transistor level schematic available for digital blocks generated with VHDL, the noise of the block is represented as equivalent current sources [25]- [28]. The active areas in the digital cells are merged as one (or several) blocks.…”

“…In the prelayout phase, a schematic of sensitive analog-and-digital aggressor blocks is available. Large digital blocks are commonly represented as equivalent current sources with a certain noise signature [25]- [28]. From the schematic, the sizes and approximate locations of the analog circuits on the chip can be estimated.…”