2021 IEEE Intl Conf on Parallel &Amp; Distributed Processing With Applications, Big Data &Amp; Cloud Computing, Sustainable Com 2021
DOI: 10.1109/ispa-bdcloud-socialcom-sustaincom52081.2021.00033
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Accuracy vs. Efficiency: Achieving both Through Hardware-Aware Quantization and Reconfigurable Architecture with Mixed Precision

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Cited by 2 publications
(3 citation statements)
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“…FBNet [19] HotNAS [16] Analytical estimation Compute a rough estimate using the processing time, the stall time and the starting time Latency FNAS [34] NASCaps [26] Energy NASCaps [26] Predictive model Build a ML model to predict the cost using architecture and dataset features Latency proxylessNAS [14] NASAIC [38] developer. For example, model prediction methods require expert knowledge to select the best features and verify them, lookup table methods also take a lot of time to build code compilation for each operation on the target hardware.…”
Section: Latencymentioning
confidence: 99%
See 1 more Smart Citation
“…FBNet [19] HotNAS [16] Analytical estimation Compute a rough estimate using the processing time, the stall time and the starting time Latency FNAS [34] NASCaps [26] Energy NASCaps [26] Predictive model Build a ML model to predict the cost using architecture and dataset features Latency proxylessNAS [14] NASAIC [38] developer. For example, model prediction methods require expert knowledge to select the best features and verify them, lookup table methods also take a lot of time to build code compilation for each operation on the target hardware.…”
Section: Latencymentioning
confidence: 99%
“…The hardware search space can be further classified as follows: Parameter configuration : The hardware search space is formalised by a group of parameter configurations. The Hardware Search Space of FNAS [34] consists of four tiled parameters of convolution. It can search for the best performing model on a given dataset and the optimised parameters needed to deploy it in an FPGA chip for deep learning.…”
Section: Search Space Of Nas On Hardware Devicesmentioning
confidence: 99%
“…Some researchers have embarked on the study of mixed-precision algorithms, which has led to many hardware accelerator designs. Chang et al ( 2021 ) designed a reconfigurable CNN processor, which can reconstruct the computing unit and the on-chip buffer according to the computing characteristics of the model with mixed-precision quantization. Jiang et al ( 2020 ) designed the PRArch accelerator architecture which support both conventional dense convolution and aggregated sparse convolution and implement mixed-precision convolution on fix-precision systolic arrays.…”
Section: Introductionmentioning
confidence: 99%