Access devices for 3D crosspoint memory

Abstract

The emergence of new nonvolatile memory (NVM) technologies—such as phase change memory, resistive, and spin-torque-transfer magnetic RAM—has been motivated by exciting applications such as storage class memory, embedded nonvolatile memory, enhanced solid-state disks, and neuromorphic computing. Many of these applications call for such NVM devices to be packed densely in vast “crosspoint” arrays offering many gigabytes if not terabytes of solid-state storage. In such arrays, access to any small subset of the array for accurate reading or low-power writing requires a strong nonlinearity in the IV characteristics, so that the currents passing through the selected devices greatly exceed the residual leakage through the nonselected devices. This nonlinearity can either be included explicitly, by adding a discrete access device at each crosspoint, or implicitly with an NVM device which also exhibits a highly nonlinear IV characteristic. This article reviews progress made toward implementing such access device functionality, focusing on the need to stack such crosspoint arrays vertically above the surface of a silicon wafer for increased effective areal density. The authors start with a brief overview of circuit-level considerations for crosspoint memory arrays, and discuss the role of the access device in minimizing leakage through the many nonselected cells, while delivering the right voltages and currents to the selected cell. The authors then summarize the criteria that an access device must fulfill in order to enable crosspoint memory. The authors review current research on various discrete access device options, ranging from conventional silicon-based semiconductor devices, to oxide semiconductors, threshold switch devices, oxide tunnel barriers, and devices based on mixed-ionic-electronic-conduction. Finally, the authors discuss various approaches for self-selected nonvolatile memories based on Resistive RAM.

Mixed-Ionic-Electronic-Conduction (MIEC)-Based Access Devices for 3D Multilayer Crosspoint Memory

“…While there is a strong incentive to make sub-arrays as large as possible, this must be traded off against the problems associated with large sub-arrays, including significant line capacitance, large worst-case resistance drop, and difficulties in enforcing compliance currents within the array [9,10]. A major issue is the aggregate leakage through all the devices other than those selected for write.…”

Reconfigurable Memristive Device Technologies

“…Select device options are described and evaluated in detail in the 2013 ITRS ERD chapter [13]. Its physics are reviewed extensively in [21] and references therein.…”

The Susceptibility of <formula formulatype="inline"> <tex Notation="TeX">${\hbox {TaO}}_{\rm x}$</tex></formula>-Based Memristors to High Dose Rate Ionizing Radiation and Total Ionizing Dose

“…Therefore, designers are continually searching for NVM technologies that can be used in radiation-hardened (rad-hard) applications. In recent years there has been a significant thrust within the semiconductor community to develop a universal or storage class memory (SCM) technology that can meet high performance memory needs [3]- [7]. Several of the emerging SCM technologies that have been identified by the International Technology Roadmap for Semiconductors (ITRS) as possible flash replacements are resistive random access memory (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM/PCRAM), and spin transfer torque magnetic RAM (STT-MRAM) [8], [9].…”