Access-aware DRAM failure-rate estimation under relaxed refresh operations

Abstract

We develop a methodology based on a series of tools that extract the elapsed time between consecutive memory

Software and hardware interfaces for approximate memories

“…Dynamic Random Access Memory (DRAM) has been used as the main memory system due to offering relatively high-density storage and low cost [113,114]. A DRAM device is accessed by the CPU through a memory controller and is organized hierarchically into modules, ranks, chips, banks, and cells [37].…”

“…The error manifestation is specific by approximation and is obtained through the characterization of the memory devices. A characterization performs several iterations exposing real or simulated hardware conditions of possible error fluctuations by adjusting parameters and verifying how the reliability of the stored data is affected [12,13,65,106,114,120]. Table 2.1 exhibits some of the major characteristics of techniques for memory approximation, where techniques that adjust parameters are nondeterministic and depend on the value of the changed parameter.…”