Acceleration of PageRank with Customized Precision Based on Mantissa Segmentation

Abstract

We describe the application of a communication-reduction technique for the PageRank algorithm that dynamically adapts the precision of the data access to the numerical requirements of the algorithm as the iteration converges. Our variable-precision strategy, using a customized precision format based on mantissa segmentation (CPMS), abandons the IEEE 754 single- and double-precision number representation formats employed in the standard implementation of PageRank, and instead handles the data in memory using a customized floating-point format. The customized format enables fast data access in different accuracy, prevents overflow/underflow by preserving the IEEE 754 double-precision exponent, and efficiently avoids data duplication, since all bits of the original IEEE 754 double-precision mantissa are preserved in memory, but re-organized for efficient reduced precision access. With this approach, the truncated values (omitting significand bits), as well as the original IEEE double-precision values, can be retrieved without duplicating the data in different formats. Our numerical experiments on an NVIDIA V100 GPU (Volta architecture) and a server equipped with two Intel Xeon Platinum 8168 CPUs (48 cores in total) expose that, compared with a standard IEEE double-precision implementation, the CPMS-based PageRank completes about 10% faster if high-accuracy output is needed, and about 30% faster if reduced output accuracy is acceptable.

Half-Precision Floating-Point Formats for PageRank: Opportunities and Challenges

“…Although these 16-bit data formats have been reported to be efficient for deep learning training, and [11] predicted the industry-wide adoption of BFloat16 format for many applications, narrow floating-point formats are highly sensitive to the application characteristics. For instance, [13] proposed a 16-bit format for PageRank that captures the top two bytes of FP64. This makes conversion to/from FP64 efficient.…”

“…Floating-point computation is fairly complex to emulate as bit-wise operations on a general-purpose instruction set [14]. It is more efficient to convert compact storage formats to a format for which arithmetic is supported by hardware, typically FP32 or FP64 [7,13]. Conversions include changes in the bit width of the exponent and rounding of the mantissa.…”

“…Mixed-precision arithmetic was previously investigated for PageRank [13]. Efficient arithmetic is ensured through efficient conversion to hardware-supported arithmetic, in this case FP64.…”

“…Three reduced-precision formats are proposed containing the top 16, 32 or 48 bits of the FP64 number: the sign bit, 11 exponent bits and a slice of the most significant mantissa bits to fill up the format. It is, however, worthwhile to use this 16-bit format only during the first power iteration [13]. After this, the format switches to 32 bits.…”

“…Conversion to native formats to perform arithmetic must be efficient in order not to offset the performance gains. Truncated formats as in [13] are easily converted, but do not provide convergence. Moreover, conversion requires a mix of 16-and 32-bit integer operations, after which the result is moved to a floating-point data type without conversion.…”