Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor

Kumaki, Takeshi; Ishizaki, Masakatsu; Koide, Tetsushi; Mattausch, Hans Jürgen; Kuroda, Yasushi; Noda, Haruhiko; Dosaka, K.; Arimoto, Kazutami; Saito, Kazunori

doi:10.1093/ietisy/e90-d.8.1312

Cited by 7 publications

(2 citation statements)

References 3 publications

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“…Since the massive‐parallel SIMD matrix consists of a simple SRAM‐based architecture, the processed data width and the magnitude of parallelism can be changed and optimized in accordance with the application needs. The MX‐1 architecture was introduced for embedded SoC in digital‐convergence mobile devices and has been used to implement multimedia applications, such as DCT processing , JPEG compression , face detection , fast multiplication , image transform , random number , and stream cipher . The MX‐1 has two types of implementation styles, an evaluation board and a simulator.…”

Section: Massive‐parallel Simd Matrix Architecturementioning

confidence: 99%

Secure data processing with massive‐parallel SIMD matrix for embedded SoC in digital‐convergence mobile devices

Kumaki

Koide

Fujino

2016

IEEJ Transactions Elec Engng

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This paper presents secure data processing with a massive-parallel single-instruction multiple-data (SIMD) matrix for embedded system-on-chip (SoC) in digital-convergence mobile devices. Recent mobile devices are required to use private-informationsecure technology, such as cipher processing, to prevent the leakage of personal information. However, this adds to the device's required specifications, especially cipher implementation for fast processing, power consumption, low hardware cost, adaptability, and end-user's operation for maintaining the safety condition. To satisfy these security-related requirements, we propose the interleaved-bitslice processing method, which combines two processing concepts (bitslice processing and interleaved processing), for novel parallel block cipher processing with five confidentiality modes on mobile processors. Furthermore, we adopt a massiveparallel SIMD matrix processor (MX-1) for interleaved-bitslice processing to verify the effectiveness of parallel block cipher implementation. As the implementation target from the Federal Information Processing Standardization-approved block ciphers, a data encryption standard (DES), triple-DES, and Advanced Encryption Standard (AES) algorithms are selected. For the AES algorithm, which is mainly studied in this paper, the MX-1 implementation has up to 93% fewer clock cycles per byte than other conventional mobile processors. Additionally, the MX-1 results are almost constant for all confidentiality modes. The practical-use energy efficiency of parallel block cipher processing with the evaluation board for MX-1 was found to be about 4.8 times higher than that of a BeagleBoard-xM, which is a single-board computer and uses the ARM Cortex-A8 mobile processor. Furthermore, to improve the operation of a single-bit logical function, we propose the development of a multi-bit logical library for interleaved-bitslice cipher processing with MX-1. Thus, the number of clock cycles is the smallest among those reported in other related-studies. Consequently, interleaved-bitslice block cipher processing with five confidentiality modes on MX-1 is effective for the implementation of parallel block cipher processing for several digital-convergence mobile devices.

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Section: Massive‐parallel Simd Matrix Architecturementioning

confidence: 99%

Secure data processing with massive‐parallel SIMD matrix for embedded SoC in digital‐convergence mobile devices

Kumaki

Koide

Fujino

2016

IEEJ Transactions Elec Engng

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“…Many papers have addressed this fine-grain parallelization opportunity [5,12]. In addition, parallelization of almost all stages, from color space conversion, over DCT to the Huffman encoding has been addressed [1,7]. Recently, with respect to the JPEG2000 codec, efficient parallelization of wavelet coding has been introduced [8].…”

Section: Related Workmentioning

confidence: 99%

Bi-criteria Pipeline Mappings for Parallel Image Processing

Benoît

Kosch

Rehn‐Sonigo

et al. 2008

Computational Science – ICCS 2008

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Abstract. Mapping workflow applications onto parallel platforms is a challenging problem, even for simple application patterns such as pipeline graphs. Several antagonistic criteria should be optimized, such as throughput/period and latency (or a combination). Typical applications include digital image processing, where images are processed in steadystate mode. In this paper, we study the bi-criteria mapping (minimizing period and latency) of the JPEG encoding on a cluster of workstations. We present an integer linear programming formulation for this NP-hard problem, and we present an in-depth performance evaluation of several polynomial heuristics.

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Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor

Kumaki

Ishizaki

Koide

et al. 2008

IEICE Transactions on Electronics

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Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor

Cited by 7 publications

References 3 publications

Secure data processing with massive‐parallel SIMD matrix for embedded SoC in digital‐convergence mobile devices

Secure data processing with massive‐parallel SIMD matrix for embedded SoC in digital‐convergence mobile devices

Bi-criteria Pipeline Mappings for Parallel Image Processing

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor

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