Acceleration Framework for FPGA Implementation of OpenVX Graph Pipelines

Taheri, Sajjad; Heo, Jin Seok; Behnam, Payman; Chen, Jeffrey; Veidenbaum, Alexander V.; Nicolau, Alexandru

doi:10.1109/fccm.2018.00061

Cited by 11 publications

(8 citation statements)

References 2 publications

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“…Third, accelerating applications with FPGAs. Previous work [25], [26], [27], [28], [29], [30], [31], [32], [33], [34], [35], [36], [3], [37], [38], [39], [40], [41], [42], [43], [44], [2], [45], [46], [47], [48], [49], [50] accelerates a broad range of applications, e.g., database and deep learning inference, using FPGAs. In contrast, we systematically benchmark HBM on the state-of-the-art FPGA regardless of the application.…”

Section: Related Workmentioning

confidence: 99%

Shuhai: Benchmarking High Bandwidth Memory On FPGAS

Wang

Huang

Zhang

et al. 2020

2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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FPGAs are starting to be enhanced with High Bandwidth Memory (HBM) as a way to reduce the memory bandwidth bottleneck encountered in some applications and to give the FPGA more capacity to deal with application state. However, the performance characteristics of HBM are still not well specified, especially in the context of FPGAs. In this paper, we bridge the gap between nominal specifications and actual performance by benchmarking HBM on a state-of-the-art FPGA, i.e., a Xilinx Alveo U280 featuring a two-stack HBM subsystem. To this end, we propose Shuhai, a benchmarking tool that allows us to demystify all the underlying details of HBM on an FPGA. FPGA-based benchmarking should also provide a more accurate picture of HBM than doing so on CPUs/GPUs, since CPUs/GPUs are noisier systems due to their complex control logic and cache hierarchy. Since the memory itself is complex, leveraging custom hardware logic to benchmark inside an FPGA provides more details as well as accurate and deterministic measurements. We observe that 1) HBM is able to provide up to 425 GB/s memory bandwidth, and 2) how HBM is used has a significant impact on performance, which in turn demonstrates the importance of unveiling the performance characteristics of HBM so as to select the best approach. Shuhai can be easily generalized to other FPGA boards or other generations of memory, e.g., HBM3, and DDR3. We will make Shuhai open-source, benefiting the community.

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Section: Related Workmentioning

confidence: 99%

Shuhai: Benchmarking High Bandwidth Memory On FPGAS

Wang

Huang

Zhang

et al. 2020

2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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“…StencilFlow [32], and other frameworks [33], [34] show how an optimized Intel OpenCL implementation is beneficial for dataflow and stream processing designs. AFFIX [35] also provides a scalable OpenCL library for vision algorithms via Intel OpenCL on FPGAs. While our work is based on stateless synchronous dataflow graphs, others [36] introduce a datacentric model for stateful dataflow multigraphs, which relies on SDAccel and Xilinx OpenCL code.…”

Section: Related Workmentioning

confidence: 99%

FLOWER: A comprehensive dataflow compiler for high-level synthesis

Amiri,

Pérard-Gayot,

Membarth

et al. 2021

Preprint

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“…Intel Open-Vino [7] provides a few example applications that are specific to Arria-10 FPGAs. Taheri et al [26] provide some initial results for FPGAs, where the main attention is the scheduling of statistical kernels (i.e., histogram). The image processing DSLs in [3,19] use similar techniques to implement user applications as a streaming pipeline.…”

Section: Related Workmentioning

confidence: 99%

“…3, where redundant computations are eliminated, and nodes are aggregated for better exploitation of locality. Memory access patterns of our abstractions entail system-level optimization strategies motivated by the OpenVX standard, such as image tiling [25] and hardware-software partitioning [26]. An abstractionbased implementation allows expressing aggregated computations as part of the reconstructed graph.…”

Section: Computational Abstractionsmentioning

confidence: 99%

HipaccVX: wedding of OpenVX and DSL-based code generation

Ozkan

Qiao

et al. 2020

J Real-Time Image Proc

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Writing programs for heterogeneous platforms optimized for high performance is hard since this requires the code to be tuned at a low level with architecture-specific optimizations that are most times based on fundamentally differing programming paradigms and languages. OpenVX promises to solve this issue for computer vision applications with a royalty-free industry standard that is based on a graph-execution model. Yet, the OpenVX ’ algorithm space is constrained to a small set of vision functions. This hinders accelerating computations that are not included in the standard. In this paper, we analyze OpenVX vision functions to find an orthogonal set of computational abstractions. Based on these abstractions, we couple an existing domain-specific language (DSL) back end to the OpenVX environment and provide language constructs to the programmer for the definition of user-defined nodes. In this way, we enable optimizations that are not possible to detect with OpenVX graph implementations using the standard computer vision functions. These optimizations can double the throughput on an Nvidia GTX GPU and decrease the resource usage of a Xilinx Zynq FPGA by 50% for our benchmarks. Finally, we show that our proposed compiler framework, called HipaccVX, can achieve better results than the state-of-the-art approaches Nvidia VisionWorks and Halide-HLS.

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Acceleration Framework for FPGA Implementation of OpenVX Graph Pipelines

Cited by 11 publications

References 2 publications

Shuhai: Benchmarking High Bandwidth Memory On FPGAS

Shuhai: Benchmarking High Bandwidth Memory On FPGAS

FLOWER: A comprehensive dataflow compiler for high-level synthesis

HipaccVX: wedding of OpenVX and DSL-based code generation

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