Accelerating vision and navigation applications on a customizable platform

Cong, Jason; Grigorian, Beayna; Reinman, Glenn; Vitanza, Marco

doi:10.1109/asap.2011.6043233

Cited by 9 publications

(7 citation statements)

References 33 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…On a platform of Xeon CPU as microprocessor, Xilinx FPGA as accelerator, TSVs as 3D integration technology and I/O blocks available in the current product, we can achieve a 7.4x speed-up and an 18.8x energy savings. A similar 3D architecture and design methodology is also used to accelerator the vision and navigation application domain [25].…”

Section: Discussionmentioning

confidence: 99%

Domain-specific processor with 3D integration for medical image processing

Cong

Guruaj

Huang

et al. 2011

ASAP 2011 - 22nd IEEE International Conference on Application-Specific Systems, Architectures and Processors

Self Cite

View full text Add to dashboard Cite

Abstract-The growth of 3D technology had led to opportunities for stacked multiprocessor-accelerator computing platforms with highbandwidth and low-latency TSV connections between them, resulting in high computing performance and better energy efficiency. This work evaluates the performance and energy benefits of such an advanced architecture and addresses associated design problems. To better utilize the reconfigurable hardware resource and to explore the opportunity of kernel sharing across applications, we propose to use a dedicated domain-specific computing platform. In particular, we have chosen medical image processing as the domain in this work to accelerate due to its growing for real-time processing demand yet inadequete performance on conventional computing architectures. A design flow is proposed in this work for the 3D multiprocessoraccelerator platform and a number of methods are applied to optimize the average performance of all the applications in the targeted domain under area and bandwidth constraints. Experiments show that the applications in this domain can gain a 7.4x speed-up and 18.8x energy savings on average running on our platform using CMP cores and domain-specific accelerators as compared to their counterparts coded in CPU only.

show abstract

Section: Discussionmentioning

confidence: 99%

Domain-specific processor with 3D integration for medical image processing

Cong

Guruaj

Huang

et al. 2011

ASAP 2011 - 22nd IEEE International Conference on Application-Specific Systems, Architectures and Processors

Self Cite

View full text Add to dashboard Cite

show abstract

“…Information on medical imaging domain can be found in [5]. Information on computer vision and navigation domain can be found in [8].…”

Section: Benchmarksmentioning

confidence: 99%

Architecture support for accelerator-rich CMPs

Cong

Ghodrat

Gill

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

Self Cite

View full text Add to dashboard Cite

This work discusses a hardware architectural support for acceleratorrich CMPs (ARC). First, we present a hardware resource management scheme for accelerator sharing. This scheme supports sharing and arbitration of multiple cores for a common set of accelerators, and it uses a hardware-based arbitration mechanism to provide feedback to cores to indicate the wait time before a particular resource becomes available. Second, we propose a light-weight interrupt system to reduce the OS overhead of handling interrupts which occur frequently in an accelerator-rich platform. Third, we propose architectural support that allows us to compose a larger virtual accelerator out of multiple smaller accelerators. We have also implemented a complete simulation tool-chain to verify our ARC architecture. Experimental results show significant performance (on average 51X) and energy improvement (on average 17X) compared to approaches using OS-based accelerator management.

show abstract

“…Using this information, the accelerators are reconfigured at a granularity of a given number of tasks (e.g. we use a task granularity of 16). For more information on configuring the neural accelerators, refer to Section III-B.…”

Section: Software Infrastructurementioning

confidence: 99%

“…Prior art in this area includes both ASIC and FPGA-based implementations of application-specific coprocessors [6], [17], including reconfigurable computing [18], [59], [16]. Single chip solutions feature accelerators that are either tightly coupled with processing core [38], [45], [73] or loosely coupled with processing cores [83], [14], [26], [55].…”

Section: A Accelerator-rich Architecturesmentioning

confidence: 99%

BRAINIAC: Bringing reliable accuracy into neurally-implemented approximate computing

Grigorian¹,

Farahpour²,

Reinman³

2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

Self Cite

View full text Add to dashboard Cite

Applications with large amounts of data, real-time constraints, ultra-low power requirements, and heavy computational complexity present significant challenges for modern computing systems, and often fall within the category of high performance computing (HPC). As such, computer architects have looked to high performance single instruction multiple data (SIMD) architectures, such as accelerator-rich platforms, for handling these workloads. However, since the results of these applications do not always require exact precision, approximate computing may also be leveraged. In this work, we introduce BRAINIAC, a heterogeneous platform that combines precise accelerators with neural-network-based approximate accelerators. These reconfigurable accelerators are leveraged in a multi-stage flow that begins with simple approximations and resorts to more complex ones as needed. We employ high-level, applicationspecific light-weight checks (LWCs) to throttle this multi-stage acceleration flow and reliably ensure user-specified accuracy at runtime. Evaluation of the performance and energy of our heterogeneous platform for error tolerance thresholds of 5%-25% demonstrates an average of 3× gain over computation that only includes precise acceleration, and 15×-35× gain over softwarebased computation.

show abstract

Accelerating vision and navigation applications on a customizable platform

Cited by 9 publications

References 33 publications

Domain-specific processor with 3D integration for medical image processing

Domain-specific processor with 3D integration for medical image processing

Architecture support for accelerator-rich CMPs

BRAINIAC: Bringing reliable accuracy into neurally-implemented approximate computing

Contact Info

Product

Resources

About