Accelerating the Analytical Modeling of Memory Level Parallelism by the Probability Analysis

Yan, Yonghong; Ling, Ming

doi:10.1109/pacrim47961.2019.8985073

Cited by 1 publication

(1 citation statement)

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“…MLP-based cost is a factor that is roughly equivalent to the cache miss latency divided by the number of misses processed in parallel, and the larger the factor, the lower the MLP. Some studies attempted to estimate the number of LLC misses being processed simultaneously as one of the performance factors [28]- [33]. These studies used the factors to speed up design space exploration.…”

Section: Related Workmentioning

confidence: 99%

A Principal Factor of Performance in Decoupled Front-End

DEGAWA,

KOIZUMI,

NAKAMURA

et al. 2023

IEICE Trans. Inf. & Syst.

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One of the performance bottlenecks of a processor is the front-end that supplies instructions. Various techniques, such as cache replacement algorithms and hardware prefetching, have been investigated to facilitate smooth instruction supply at the front-end and to improve processor performance. In these approaches, one of the most important factors has been the reduction in the number of instruction cache misses. By using the number of instruction cache misses or derived factors, previous studies have explained the performance improvements achieved by their proposed methods. However, we found that the number of instruction cache misses does not always explain performance changes well in modern processors. This is because the front-end in modern processors handles subsequent instruction cache misses in overlap with earlier ones. Based on this observation, we propose a novel factor: the number of miss regions. We define a region as a sequence of instructions from one branch misprediction to the next, while we define a miss region as a region that contains one or more instruction cache misses. At the boundary of each region, the pipeline is flushed owing to a branch misprediction. Thus, cache misses after this boundary are not handled in overlap with cache misses before the boundary. As a result, the number of miss regions is equal to the number of cache misses that are processed without overlap. In this paper, we demonstrate that the number of miss regions can well explain the variation in performance through mathematical models and simulation results. The results show that the model explains cycles per instruction with an average error of 1.0% and maximum error of 4.1% when applying an existing prefetcher to the instruction cache. The idea of miss regions highlights that instruction cache misses and branch mispredictions interact with each other in processors with a decoupled front-end. We hope that considering this interaction will motivate the development of fast performance estimation methods and new microarchitectural methods.

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Section: Related Workmentioning

confidence: 99%