Accelerating search and recognition workloads with SSE 4.2 string and text processing instructions

Abstract

Today's information is increasing rapidly, doubling every three years. Consequently, the search and recognition stages in computer applications will consume a growing portion of the total CPU time. The SSE 4.2 instruction set, first implemented in Intel's Core i7, provides string and text processing instructions (STTNI) that utilize SIMD operations for processing character data. Though originally conceived for accelerating string, text, and XML processing, the powerful new capabilities of these instructions are useful outside of these domains, and it is worth revisiting the search and recognition stages of numerous applications to utilize STTNI to improve performance. In this paper, we explored the feasibility and potential benefit of using STTNI to improve the CPU and memory performance of search-and-recognition applications. We optimized four benchmark applications -cache simulation, B+tree search algorithm, template matching, Basic Local Alignment Search Tool (BLAST) -with STTNI, and the new applications outperform their respective original implementations by a factor of 1.4x to 13x.

Genome matching on modern architectures

“…However, this is overshadowed by the value of being able to perform MMX operations on the wider SSE registers. Other SSE2 extensions include a set of cache-control instructions intended primarily to minimize cache pollution when processing indefinite streams of information, and a sophisticated complement of numeric format conversion instructions [9], [10].…”

“…In order to further improve the performance we added code to take advantage of the SSE 4.2 STTNI instructions for string comparison [10]. Some more recent CPUs from Intel feature this hardware capability to compare strings.…”