Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis

Hughes, Clay; Li, Tao

doi:10.1109/iiswc.2008.4636101

Cited by 22 publications

(14 citation statements)

References 22 publications

(36 reference statements)

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“…Table 1 summarizes which microarchitectural parameters can or cannot be changed during design space exploration without the need for recomputing the statistical profile. An important improvement over prior work in statistical simulation [6], [11], [13], [18], [19], [20] is that the cache statistics are largely microarchitecture-independent. As such, we can explore most of the memory hierarchy design space from a single statistical profile.…”

Section: Design Space Exploration Using Statistical Simulationmentioning

confidence: 97%

“…This paper considered multiprogram workloads only and showed that given the enhancements proposed in this paper, CMP resource sharing can be modeled accurately in statistical simulation for multiprogram workloads. Combining it with the Nussbaum and Smith [19] and Hughes and Li [13] approaches will make statistical simulation viable for modeling multithreaded workloads running on CMPs with shared resources. Second, this paper made a first but important step toward making the statistical profile microarchitecture-independent.…”

Section: Discussionmentioning

confidence: 99%

“…To do so, they extended statistical simulation to model synchronization and accesses to shared memory. Hughes and Li [13] more recently introduced synchronized statistical flow graphs that incorporate interthread synchronization. Cache behavior is still modeled based on cache miss rates though; by consequence, they are unable to model shared caches as observed in modern CMPs.…”

Section: Statistical Modelingmentioning

confidence: 99%

“…Previous work has been exploring the statistical simulation paradigm extensively for uniprocessor simulation [6], [11], [18], [20], and one earlier study [19] and one more recent study [13] applied statistical simulation to multithreaded workloads running on shared memory multiprocessor systems. None of this prior work addresses the modeling of shared resources in chip multiprocessors though.…”

Section: Introductionmentioning

confidence: 99%

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Chip Multiprocessor Design Space Exploration through Statistical Simulation

Genbrugge

Eeckhout

2009

IEEE Trans. Comput.

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Abstract-Developing fast chip multiprocessor simulation techniques is a challenging problem. Solving this problem is especially valuable for design space exploration purposes during the early stages of the design cycle where a large number of design points need to be evaluated quickly. This paper studies statistical simulation as a fast simulation technique for chip multiprocessor (CMP) design space exploration. The idea of statistical simulation is to measure a number of program execution characteristics from a real program execution through profiling, to generate a synthetic trace from it, and simulate that synthetic trace as a proxy for the original program. The important benefit is that the synthetic trace is much shorter compared to a real program trace, which leads to substantial simulation speedups. This paper enhances state-of-the-art statistical simulation: 1) by modeling the memory address stream behavior in a more microarchitecture-independent way and 2) by modeling a program's time-varying execution behavior. These two enhancements enable accurately modeling resource conflicts in shared resources as observed in the memory hierarchy of contemporary chip multiprocessors when multiple programs are coexecuting on the CMP. Our experimental evaluation using the SPEC CPU benchmarks demonstrates average prediction error of 7.3 percent across a range of CMP configurations while varying the number of cores and memory hierarchy configurations.

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Section: Design Space Exploration Using Statistical Simulationmentioning

confidence: 97%

Section: Discussionmentioning

confidence: 99%

Section: Statistical Modelingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Chip Multiprocessor Design Space Exploration through Statistical Simulation

Genbrugge

Eeckhout

2009

IEEE Trans. Comput.

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“…To reduce simulation overhead for CMP design, Genbrugge and Eeckhout proposed several statistical quantities to capture the behavior of cache access and shared resource contentions that are critical to the performance of multi-programmed programs running on CMPs [13,14]. Hughes and Li proposed to leverage statistical characteristics that capture the behaviors of memory sharing and inter-thread synchronization when constructing synthetic multi-threaded programs [16].…”

Section: Fast Simulation Techniquesmentioning

confidence: 99%

ArchRanker: A ranking approach to design space exploration

Guo

Tang

Temam

et al. 2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

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Architectural Design Space Exploration (DSE) is a notoriously difficult problem due to the exponentially large size of the design space and long simulation times. Previously, many studies proposed to formulate DSE as a regression problem which predicts architecture responses (e.g., time, power) of a given architectural configuration. Several of these techniques achieve high accuracy, though often at the cost of significant simulation time for training the regression models.We argue that the information the architect mostly needs during the DSE process is whether a given configuration will perform better than another one in the presences of design constraints, or better than any other one seen so far, rather than precisely estimating the performance of that configuration.Based on this observation, we propose a novel rankingbased approach to DSE where we train a model to predict which of two architecture configurations will perform best. We show that, not only this ranking model more accurately predicts the relative merit of two architecture configurations than an ANN-based state-of-the-art regression model, but also that it requires much fewer training simulations to achieve the same accuracy, or that it can be used for and is even better at quantifying the performance gap between two configurations.We implement the framework for training and using this model, called ArchRanker, and we evaluate it on several DSE scenarios (unicore/multicore design spaces, and both time and power performance metrics). We try to emulate as closely as possible the DSE process by creating constraint-based scenarios, or an iterative DSE process. We find that ArchRanker makes 29.68% to 54.43% fewer incorrect predictions on pairwise relative merit of configurations (tested with 79,800 configuration pairs) than an ANN-based regression model across all DSE scenarios considered (values averaged over all benchmarks for each scenario). We also find that, to achieve the same accuracy as ArchRanker, the ANN often requires three times more training simulations.

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