Accelerating molecular dynamics simulations with configurable circuits

Gu, Yongfeng; VanCourt, T.; Herbordt, Martin C.

doi:10.1049/ip-cdt:20050182

Cited by 42 publications

(53 citation statements)

References 21 publications

(18 reference statements)

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“…The system uses the x G y 6 method to find interacting pairs. [7] is another work in which the entire velocity Verlet algorithm is considered. This work is similar to [3] in that both implementations perform all steps of the algorithm in hardware using fixed-point arithmetic, only nonbonded force calculation is implemented, this nonbonded force calculation is performed with table lookup and interpolation, and, it seems, the interaction pairs are found using the x H y 6 approach.…”

Section: Comparison To Related Workmentioning

confidence: 99%

“…This hardware/software approach to acceleration is the key to developing a more complete simulation system than previous acceleration efforts that moved all tasks of the simulation into hardware [3,7]. It takes into account the fact that not all tasks in a large scientific program, such as a program for MD simulation, are good candidates for acceleration.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers

Scrofano

Gokhale

Trouw

et al. 2006

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

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Section: Comparison To Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers

Scrofano

Gokhale

Trouw

et al. 2006

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

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show abstract

“…9 We have found that the acceleratable kernel not only comprises more than 90 percent of execution time with ProtoMol, but the modularity enables straightforward integration of an FPGA accelerator. 10 …”

Section: Methods 4: Living With Amdahl's Lawmentioning

confidence: 99%

“…While most MD applications require more than the 24 bits provided by a single-precision floating point, they might not need double precision (53 bits). 10 Sample HPC/FPGA solution-We return to the modeling molecular interactions case study to illustrate the tradeoff between PE complexity and degree of parallelism. That study examined six different models describing intermolecular forces.…”

Section: Methods 8:use Appropriate Arithmetic Precisionmentioning

confidence: 99%

Achieving High Performance with FPGA-Based Computing

et al. 2007

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Numerous application areas, including bioinformatics and computational biology, demand increasing amounts of processing capability. In many cases, the computation cores and data types are suited to field-programmable gate arrays. The challenge is identifying the design techniques that can extract high performance potential from the FPGA fabric.Accelerating high-performance computing (HPC) applications with field-programmable gate arrays (FPGAs) can potentially deliver enormous performance. A thousand-fold parallelism is possible, especially for low-precision computations. Moreover, since control is configured into the logic itself, overhead instructions-such as array indexing and loop computationsneed not be emulated, and every operation can deliver payload.At the same time, using FPGAs presents significant challenges 1 including low operating frequency-an FPGA clocks at one-tenth that of a high-end microprocessor. Another is simply Amdahl's law: To achieve the speedup factors required for user acceptance of a new technology (preferably 50 times), 2 at least 98 percent of the target application must lend itself to substantial acceleration. As a result, HPC/FPGA application performance is unusually sensitive to the implementation's quality.The problem of achieving significant speedups on a new architecture without expending exorbitant development effort, and while retaining flexibility, portability, and maintainability, is a classic one. In this case, accelerating HPC applications with FPGAs is similar to that of porting uniprocessor applications to massively parallel processors, with two key distinctions:• FPGAs are far more different from uniprocessors than MPPs are from uniprocessors, and• the process of parallelizing code for MPPs, while challenging, is still better understood and supported than porting codes to FPGAs.Lawrence Snyder stated the three basic parameters for the MPP portability problem. 3 First, a parallel solution using P processors can improve the best sequential solution by a factor of P, at most. Second, HPC problems tend to have third-or fourth-order complexity, and so parallel computation, while essential, offers only modest benefits. Third, "the whole force of parallelism must be transferred to the problem, not converted to 'heat' of implementational overhead."Researchers have addressed the portability problem periodically over the past 30 years, with well-known approaches involving language design, optimizing compilers, emulation, software engineering tools and methods, and function and application libraries. It is generally agreed that compromises are required: Either restrict the variety of architectures or scope of application, or bound expectations of performance or ease of implementation.

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“…All these hardware systems are specialized ASIC based solutions for specific N-body applications. Reconfigurable systems utilizing FPGAs have been developed in [23], [24], [25], [26], [27]. Most of them are also customized for a particular interaction function.…”

Section: Scientific Application: N-body Problemsmentioning

confidence: 99%

An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization

Kim

Deng

Mangalagiri

et al. 2009

IEEE Trans. Comput.

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Abstract-This paper describes TANOR, an automated framework for designing hardware accelerators for numerical computation on reconfigurable platforms. Applications utilizing numerical algorithms on large-size data sets require high-throughput computation platforms. The focus is on N-body interaction problems which have a wide range of applications spanning from astrophysics to molecular dynamics. The TANOR design flow starts with a MATLAB description of a particular interaction function, its parameters, and certain architectural constraints specified through a graphical user interface. Subsequently, TANOR automatically generates a configuration bitstream for a target FPGA along with associated drivers and control software necessary to direct the application from a host PC. Architectural exploration is facilitated through support for fully custom fixed-point and floating point representations in addition to standard number representations such as single precision floating point. Moreover, TANOR enables joint exploration of algorithmic and architectural variations in realizing efficient hardware accelerators. TANOR's capabilities have been demonstrated for three different N-body interaction applications: the calculation of gravitational potential in astrophysics, the diffusion or convolution with Gaussian kernel common in image processing applications, and the force calculation with vector-valued kernel function in molecular dynamics simulation. Experimental results show that TANOR-generated hardware accelerators achieve lower resource utilization without compromising numerical accuracy, in comparison to other existing custom accelerators.

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Accelerating molecular dynamics simulations with configurable circuits

Cited by 42 publications

References 21 publications

Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers

Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers

Achieving High Performance with FPGA-Based Computing

An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization

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