Accelerating Millions of Short Reads Mapping on a Heterogeneous Architecture with FPGA Accelerator

Tang, Wen; Wang, Wendi; Duan, Bo; Zhang, Chunming; Tan, Guangming; Zhang, Peiheng; Sun, Ninghui

doi:10.1109/fccm.2012.39

Cited by 47 publications

(11 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In [26], the authors introduce a FPGA-based solution to the short read mapping problem which achieves a 31x speedup versus BOWTIE on eight CPU cores. In [27], the speedup of their accelerator over a six-cores CPU ranges from 22.2x to 42.9x. In [28], the author focus on long reads mapping: their FPGA-based platform achieves a 1.8x-3.2x speedup versus the BWA-SW aligner.…”

Section: Related Workmentioning

confidence: 99%

“…A significant number of papers have been published that either use FPGAs (see, e.g., [1], [9], [24], [25], [25], [26], [27], [28], [29], [30], [31]) or GPUs (see, e.g., [32], [33]). For instance in [24], the authors propose a hybrid system for short read mapping utilizing both FPGA-based hardware and CPU-based software: the hardware implements parallel block-wise alignment structure to approximate the conventional dynamic programming algorithm.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

<sc>FHAST</sc>: FPGA-Based Acceleration of <sc>Bowtie</sc> in Hardware

Fernandez

Villarreal

Lonardi

et al. 2015

IEEE/ACM Trans. Comput. Biol. and Bioinf.

View full text Add to dashboard Cite

Abstract-While the sequencing capability of modern instruments continues to increase exponentially, the computational problem of mapping short sequenced reads to a reference genome still constitutes a bottleneck in the analysis pipeline. A variety of mapping tools (e.g., BOWTIE, BWA) is available for general-purpose computer architectures. These tools can take many hours or even days to deliver mapping results, depending on the number of input reads, the size of the reference genome and the number of allowed mismatches or insertion/deletions, making the mapping problem an ideal candidate for hardware acceleration. In this paper, we present FHAST (FPGA hardware accelerated sequence-matching tool), a drop-in replacement for BOWTIE that uses a hardware design based on field programmable gate arrays (FPGA). Our architecture masks memory latency by executing multiple concurrent hardware threads accessing memory simultaneously. FHAST is composed by multiple parallel engines to exploit the parallelism available to us on an FPGA. We have implemented and tested FHAST on the Convey HC-1 and later ported on the Convey HC-2ex, taking advantage of the large memory bandwidth available to these systems and the shared memory image between hardware and software. A preliminary version of FHASTrunning on the Convey HC-1 achieved up to 70x speedup compared to BOWTIE (single-threaded). An improved version of FHAST running on the Convey HC-2ex FPGAs achieved up to 12x fold speed gain compared to BOWTIE running eight threads on an eight-core conventional architecture, while maintaining almost identical mapping accuracy. FHAST is a drop-in replacement for BOWTIE, so it can be incorporated in any analysis pipeline that uses BOWTIE (e.g., TOPHAT).

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

<sc>FHAST</sc>: FPGA-Based Acceleration of <sc>Bowtie</sc> in Hardware

Fernandez

Villarreal

Lonardi

et al. 2015

IEEE/ACM Trans. Comput. Biol. and Bioinf.

View full text Add to dashboard Cite

show abstract

“…Tang et al (2012) have accelerated short read mapping and achieved 42× speed-up over software PerM (Chen et al, 2009). Aluru and Jammula (2014) review the different acceleration techniques used for genome assembly.…”

Section: Related Work With Fpga-based Accelerationmentioning

confidence: 99%

Hardware acceleration of de novo genome assembly

Varma

Paul

Balakrishnan

et al. 2017

IJES

View full text Add to dashboard Cite

Abstract:The cost of genome assembly has gone down drastically with the advent of next generation sequencing technologies. These new sequencing technologies produce large amounts of DNA fragments. Software programs are used to construct the genome from these DNA fragments. The assembly programs take significant amount of time to execute. To reduce the execution time, these programs are being parallelised to take advantage of many cores available in present day processor chips. Further, hardware accelerators have been developed which when used along with processors speed up the execution. Velvet is a commonly used software for de novo assembly. We propose a novel method to reduce the overall time of assembly by using FPGAs. In this method, we perform pre-processing of these short reads on FPGAs and process the output using Velvet to reduce the overall time for assembly. We show that using our technique we can get significant speed-ups.

show abstract

“…In recent years, there are several new studies [31][32][33][34][35][36] that focus on short sequence alignment on new generation Virtex-5 or Virtex-6 FPGA-based system. Those literatures only consider the hardware implementation for scoring stage in the SW algorithm (without backtracking) and only support short DNA read mapping less than 512 base pairs, except for the last one [36], which implemented the longer read alignment with the length up to 4096 base pairs.…”

mentioning

confidence: 99%

FPGASW: Accelerating Large-Scale Smith–Waterman Sequence Alignment Application with Backtracking on FPGA Linear Systolic Array

Xia

Zou

Liu

et al. 2017

Interdiscip Sci Comput Life Sci

View full text Add to dashboard Cite

The Smith-Waterman (SW) algorithm based on dynamic programming is a well-known classical method for high precision sequence matching and has become the gold standard to evaluate sequence alignment software. In this paper, we propose fine-grained parallelized SW algorithms using affine gap penalty and implement a parallel computing structures to accelerating the SW with backtracking on FPGA platform. We analysis the dynamic parallel computing features of anti-diagonal elements and storage expansion problem resulting from backtracking stage, and propose a series of optimization strategies to eliminate data dependency, reduce storage requirements, and overlap memory access latency. Our implementation is capable of supporting multi-type, large-scale biological sequence alignment applications. We obtain a speedup between 3.6 and 25.2 over the typical SW algorithm running on a general-purpose computer configured with an Intel Core i5 3.2 GHz CPU. Moreover, our work is superior to other FPGA implementations in both array size and clock frequency, and the experiment results show that it can get a performance closed to that of the latest GPU implementation, but the power consumption is only about 26% of that of the GPU platforms.

show abstract

Accelerating Millions of Short Reads Mapping on a Heterogeneous Architecture with FPGA Accelerator

Cited by 47 publications

References 10 publications

<sc>FHAST</sc>: FPGA-Based Acceleration of <sc>Bowtie</sc> in Hardware

<sc>FHAST</sc>: FPGA-Based Acceleration of <sc>Bowtie</sc> in Hardware

Hardware acceleration of de novo genome assembly

FPGASW: Accelerating Large-Scale Smith–Waterman Sequence Alignment Application with Backtracking on FPGA Linear Systolic Array

Contact Info

Product

Resources

About