Accelerating Large-Scale Graph Neural Network Training on Crossbar Diet

Ogbogu, Chukwufumnanya; Arka, Aqeeb Iqbal; Joardar, Biresh Kumar; Doppa, Janardhan Rao; Li, Hai; Chakrabarty, Krishnendu; Pande, Partha Pratim

doi:10.1109/tcad.2022.3197342

Cited by 7 publications

(2 citation statements)

References 31 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…[46] proposes GCoD, a GCN algorithm and accelerator Co-Design framework, involving a two-pronged accelerator with a separated engine to process dense and sparse workloads. Some previous studies focus on accelerating GNN training [48,49,10,50]. GraphACT [48] introduces an FPGA-based accelerator with a subgraph-based algorithm for Graph Convolutional Networks (GCNs) training.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

LL-GNN: Low Latency Graph Neural Networks on FPGAs for Particle Detectors

Que¹,

Loo²,

Fan³

et al. 2022

Preprint

View full text Add to dashboard Cite

This work proposes a novel reconfigurable architecture for low latency Graph Neural Network (GNN) design specifically for particle detectors. Accelerating GNNs for particle detectors is challenging since it requires sub-microsecond latency to deploy the networks for online event selection in the Level-1 triggers at the CERN Large Hadron Collider experiments. This paper proposes a custom code transformation with strength reduction for the matrix multiplication operations in the interaction-network based GNNs with fully connected graphs, which avoids the costly multiplication of the adjacency matrix with the input feature matrix. It exploits sparsity patterns as well as binary adjacency matrices, and avoids irregular memory access, leading to a reduction in latency and improvement in hardware efficiency. In addition, we introduce an outer-product based matrix multiplication approach which is enhanced by the strength reduction for low latency design. Also, a fusion step is introduced to further reduce the design latency. Furthermore, an GNN-specific algorithm-hardware co-design approach is presented which not only finds a design with a much better latency but also finds a high accuracy design under a given latency constraint. Finally, a customizable template for this low latency GNN hardware architecture has been designed and open-sourced, which enables the generation of low-latency FPGA designs with efficient resource utilization using a high-level synthesis tool. Evaluation results show that our FPGA implementation is up to 24 times faster and consumes up to 45 times less power than a GPU implementation. Compared to our previous FPGA implementations, this work achieves 6.51 to 16.7 times lower latency. Moreover, the latency of our FPGA design is sufficiently low to enable deployment of GNNs in a sub-microsecond, real-time collider trigger system, enabling it to benefit from improved accuracy.

show abstract

Section: Related Workmentioning

confidence: 99%

“…[10] proposes HP-GNN which maps GNN training on the CPU-FPGA platform automatically. DietGNN [50], a crossbaraware pruning technique, is proposed to accelerate the training of large-scale GNNs.…”

Section: Related Workmentioning

confidence: 99%