Accelerating computing with the cell broadband engine processor

Crawford, Catherine H.; Henning, Paul; Kistler, Michael; Wright, Cornell

doi:10.1145/1366230.1366234

Cited by 34 publications

(27 citation statements)

References 5 publications

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“…Some runtime systems were designed to address multicore and accelerators architectures [6,12,16]. Most approaches adopt an interface similar to CHARM++'s asynchronous OFFLOAD API.…”

Section: Related Workmentioning

confidence: 99%

StarPU: A Unified Platform for Task Scheduling on Heterogeneous Multicore Architectures

Augonnet

Thibault

Namyst

et al. 2009

Lecture Notes in Computer Science

387

462

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Abstract. In the field of HPC, the current hardware trend is to design multiprocessor architectures that feature heterogeneous technologies such as specialized coprocessors (e.g., Cell/BE SPUs) or data-parallel accelerators (e.g., GPGPUs). Approaching the theoretical performance of these architectures is a complex issue. Indeed, substantial efforts have already been devoted to efficiently offload parts of the computations. However, designing an execution model that unifies all computing units and associated embedded memory remains a main challenge. We have thus designed STARPU, an original runtime system providing a highlevel, unified execution model tightly coupled with an expressive data management library. The main goal of STARPU is to provide numerical kernel designers with a convenient way to generate parallel tasks over heterogeneous hardware on the one hand, and easily develop and tune powerful scheduling algorithms on the other hand. We have developed several strategies that can be selected seamlessly at run time, and we have demonstrated their efficiency by analyzing the impact of those scheduling policies on several classical linear algebra algorithms that take advantage of multiple cores and GPUs at the same time. In addition to substantial improvements regarding execution times, we obtained consistent superlinear parallelism by actually exploiting the heterogeneous nature of the machine.

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“…Some runtime systems were designed to address multicore and accelerators architectures [6,12,16]. Most approaches adopt an interface similar to CHARM++'s asynchronous OFFLOAD API.…”

Section: Related Workmentioning

confidence: 99%

StarPU: A Unified Platform for Task Scheduling on Heterogeneous Multicore Architectures

Augonnet

Thibault

Namyst

et al. 2009

Lecture Notes in Computer Science

387

462

View full text Add to dashboard Cite

show abstract

“…Our framework implements data transfers and workload scheduling transparently, while adapting the parameters of data streaming and task scheduling to the application's requirements at runtime, thereby relieving programmers of some significant programming effort. By contrast, previously developed data distribution and task management libraries for asymmetric accelerator-based architectures [19], delegate parameterization of data transfers and workload scheduling to the programmer.…”

Section: Resource-constrained Well-provisioned Acceleratorsmentioning

confidence: 99%

Designing Accelerator-Based Distributed Systems for High Performance

Rafique

Butt

Nikolopoulos

2010

2010 10th IEEE/ACM International Conference on Cluster, Cloud and Grid Computing

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Abstract-Multi-core processors with accelerators are becoming commodity components for high-performance computing at scale. While accelerator-based processors have been studied in some detail, the design and management of clusters based on these processors have not received the same focus. In this paper, we present an exploration of four design and resource management alternatives, which can be used on largescale asymmetric clusters with accelerators. Moreover, we adapt the popular MapReduce programming model to our proposed configurations. We enhance MapReduce with new dynamic data streaming and workload scheduling capabilities, which enable application writers to use asymmetric acceleratorbased clusters without being concerned with the capabilities of individual components. We present an evaluation of the presented designs in a physical setting and show that our designs can provide significant performance advantages. Compared to a standard static MapReduce design, we achieve 62.5%, 73.1%, and 82.2% performance improvement using accelerators with limited general-purpose resources, well-provisioned shared general-purpose resources, and well-provisioned dedicated general-purpose resources, respectively.

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“…Inter-processor synchronization implemented using ISA-specific atomic operations is particularly problematic, as atomic operations are not uniform across different processor families [2]. Some processors, such as the MicroBlaze, have no built-in atomic oper- [3,4], and ReconOS [5] resolve these differences using remote-procedure call (RPC) mechanisms that invoke services on a host processor. Although flexible, RPC mechanisms are typically implemented using heavyweight interrupt and exception mechanisms.…”

Section: Hthreads Heterogeneous Microkernelmentioning

confidence: 99%

Automating the design of mLUT MPSoPC FPGAs in the cloud

Cartwright

Fahkari

et al. 2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

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Modern platform FPGAs are over the million-LUT level, large enough to support complete heterogeneous Multiprocessor System-On-Chips (MPSoCs). Constructing systems with 10's of processors is currently feasible using existing manual methods within vendor-specific CAD tools. However these manual, by-hand, approaches will not be feasible for constructing future systems with 100's to 1,000's of processors. Instead, new automated system assembly approaches will be required to handle these levels of system complexity and diversity. In this paper we present a new automated design flow for creating such next generation heterogeneous MPSoCs. An integral part of the MPSoPC system created is the inclusion of a general purpose PThreadscompliant HW/SW co-designed operating system and heterogeneous compiler. Our design flow has been placed in the cloud and is freely accessible across the Internet.

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Accelerating computing with the cell broadband engine processor

Cited by 34 publications

References 5 publications

StarPU: A Unified Platform for Task Scheduling on Heterogeneous Multicore Architectures

StarPU: A Unified Platform for Task Scheduling on Heterogeneous Multicore Architectures

Designing Accelerator-Based Distributed Systems for High Performance

Automating the design of mLUT MPSoPC FPGAs in the cloud

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