Accelerated image processing on FPGAs

Draper, Bruce A.; Beveridge, J. Ross; Böhm, A. P. Wim; Ross, Charles A.; Chawathe, M.

doi:10.1109/tip.2003.819226

Cited by 112 publications

(44 citation statements)

References 22 publications

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“…We need to improve its throughput and latency, which can be accomplished by simultaneously processing multiple adjacent rows [26]. This requires multiple pixels to be input per clock cycle and exploits the fact that the windows for vertically adjacent outputs overlap significantly, as can be seen in Fig.…”

Section: B Unfolding Retimed Architecturementioning

confidence: 99%

A High Speed Architecture for Lifting-based 2-D Cohen-Daubechies-Feauveau (5,3) Discrete Wavelet Transform used in JPEG2000

Lone

ud-Din

2017

IJATES

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Abstract-For real-time applications, efficient VLSI implementation of DWT is desired. In this paper, DWT architecture based on retiming for pipelining and unfolding is presented. The architecture is based on lifting one-dimensional CohenDaubechies-Feauveau (CDF) (5,3) wavelet filter, which is easily extended to 2-D implementation. It consists of low complexity and easily repeatable components. This paper is focused on the critical path minimization and throughput optimization at the same time. The architecture has been implemented on Virtex 6 Xilinx FPGA platform. The implementation results show that the critical path is minimized four to five times, while throughput is doubled, making the overall architecture approximately ten times faster when compared with the conventional lifting-based DWT architecture. Further with parallel implementation, the throughput has doubled without any increase in number of row buffers, implying that the architecture is memory efficient as well. The even and odd rows of the image are scanned in parallel fashion. To perform the 2-D DWT transform of an image of size 15 Megapixels, it takes 16.86 ms, which implies 59 images of that size can be processed in one second. This can be utilized for real-time video processing applications even for high resolution videos.

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Section: B Unfolding Retimed Architecturementioning

confidence: 99%

A High Speed Architecture for Lifting-based 2-D Cohen-Daubechies-Feauveau (5,3) Discrete Wavelet Transform used in JPEG2000

Lone

ud-Din

2017

IJATES

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“…Moreover, FPGAs are generally the first devices to be implemented on the state-of-art silicon technology. Therefore, even if FPGAs were initially created for developing little glue-logic, they currently often represent the core of various systems in different fields (e.g., [9][10][11][12][13][14] The software environment for friendly designing, simulating and testing is Altera's Quartus II™. Fig.…”

Section: Fpga-based Hardware Implementationmentioning

confidence: 99%

A Visual Inspection System for Rail Detection and Tracking in Real Time Railway Maintenance

Ruvo¹,

Ruvo²,

Distante³

et al. 2008

TOCSJ

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Rail inspection is an essential task in railway maintenance and is periodically needed. Inspection is manually operated by trained human operator walking along the track searching for visual anomalies. This monitoring is unacceptable for slowness and lack of objectivity. This paper deals with a patented Visual Inspection System for Railway maintenance, devoted to different tasks. Here, its Rail Detection & Tracking Block (RD&TB) is presented.RD&TB detects and tracks, into the acquired video sequence the rail head, by this way, notably reducing the area to be analyzed and inspected by other modules of VISyR. Thanks to its hardware implementation, RD&TB performs its task in 5.71 μs with an accuracy of 98.5%, allowing an on-the-fly analysis of a video sequence acquired up at 190 km/h. RD&TB is highly flexible and configurable, since it is based on classifiers that can be easily reconfigured in function of different type of rails.

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“…The most important idea behind the smart camera architecture is to collect video data and then analyze, interpret and reduce the information before it leaves the camera. To ensure realtime processing, the computation architecture used in the camera traditionally are VLIW processor and more recently it has been shown that programmable logic (FPGAs) are more efficient in implementing RTVPS systems [4] [5]. Based on this fact, we have selected FPGA as the target architecture for the design environment presented in this paper.…”

Section: Introductionmentioning

confidence: 99%

C++ based System Synthesis of Real-Time Video Processing Systems targeting FPGA Implementation

Lawal

O’Nils

Thörnberg

2007

2007 IEEE International Parallel and Distributed Processing Symposium

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Accelerated image processing on FPGAs

Cited by 112 publications

References 22 publications

A High Speed Architecture for Lifting-based 2-D Cohen-Daubechies-Feauveau (5,3) Discrete Wavelet Transform used in JPEG2000

A High Speed Architecture for Lifting-based 2-D Cohen-Daubechies-Feauveau (5,3) Discrete Wavelet Transform used in JPEG2000

A Visual Inspection System for Rail Detection and Tracking in Real Time Railway Maintenance

C++ based System Synthesis of Real-Time Video Processing Systems targeting FPGA Implementation

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