Accelerated Charged Particle Tracking with Graph Neural Networks on FPGAs

Heintz, Aneesh; Razavimaleki, Vesal; Duarte, Javier; DeZoort, Gage; Ojalvo, Isobel; Thais, Savannah; Atkinson, Markus; Neubauer, Mark; Gray, Lindsey; Jindariani, Sergo; Tran, Nhan; Harris, Philip; Rankin, Dylan; Aarrestad, Thea; Loncar, Vladimir; Pierini, Maurizio; Summers, Sioni; Ngadiuba, Jennifer; Liu, Mia; Kreinar, Edward; Wu, Zhenbin

doi:10.48550/arxiv.2012.01563

Cited by 13 publications

(13 citation statements)

References 26 publications

(43 reference statements)

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“…Our current work extends this by allowing more generic IN architectures to be converted with hls4ml, permitting the specification of a variable graph adjacency matrix as input, and supporting per-node or per-edge outputs as well as per-graph outputs. This paper also supersedes an earlier version of this work in Heintz et al (2020).…”

Section: Related Worksupporting

confidence: 67%

Graph Neural Networks for Charged Particle Tracking on FPGAs

Elabd,

Razavimaleki,

Huang

et al. 2021

Preprint

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The determination of charged particle trajectories in collisions at the CERN Large Hadron Collider (LHC) is an important but challenging problem, especially in the high interaction density conditions expected during the future high-luminosity phase of the LHC (HL-LHC). Graph neural networks (GNNs) are a type of geometric deep learning algorithm that has successfully been applied to this task by embedding tracker data as a graph-nodes represent hits, while edges represent possible track segments-and classifying the edges as true or fake track segments. However, their study in hardware-or software-based trigger applications has been limited due to their large computational cost. In this paper, we introduce an automated translation workflow, integrated into a broader tool called hls4ml, for converting GNNs into firmware for field-programmable gate arrays (FPGAs). We use this translation tool to implement GNNs for charged particle tracking, trained using the TrackML challenge dataset, on FPGAs with designs targeting different graph sizes, task complexites, and latency/throughput requirements. This work could enable the inclusion of charged particle tracking GNNs at the trigger level for HL-LHC experiments.

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Section: Related Worksupporting

confidence: 67%

Graph Neural Networks for Charged Particle Tracking on FPGAs

Elabd,

Razavimaleki,

Huang

et al. 2021

Preprint

Self Cite

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“…Separately, the availability of the TrackML datasets ( [11] for the Accuracy phase and [10] for this Throughput phase) has been extremely useful to facilitate the collaboration of experts which are usually working within their own experimental team. It is being used for further studies like track seeds finding with similarity hashing [20] or classification with deep learning [21], investigating the use of cluster shape to help seeding [22], investigating tracking with graph net-works [23,24,25,26,27] (including with FPGA [28] ), investigating tracking with simulated annealing on a D-Wave quantum computer [29,30] or Quantum Edge Network [31,32,33], and building a complete generic tracking pipeline [34].…”

Section: Discussionmentioning

confidence: 99%

The Tracking Machine Learning Challenge: Accuracy Phase

Amrouche¹,

Basara²,

Calafiura³

et al. 2019

The Springer Series on Challenges in Machine Learning

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“…So far, new development has been focused on the Vivado HLS [7] back-end targeting Xilinx FPGAs. We have demonstrated this workflow for fully-connected, or dense, neural networks (DNNs) [1], binary and ternary networks [8], boosted decision trees [9], and graph neural networks [10,11]. The hls4ml library accepts models from TENSORFLOW [12], KERAS [13], PYTORCH [14], and via the ONNX interface [15].…”

Section: Introductionmentioning

confidence: 99%

“…Nevertheless, complex architectures can be supported, as discussed in Ref. [10,11] in the case of graph neural networks.…”

Section: Introductionmentioning

confidence: 99%

Fast convolutional neural networks on FPGAs with hls4ml

Aarrestad,

Loncar,

Ghielmetti

et al. 2021

Preprint

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We introduce an automated tool for deploying ultra low-latency, low-power deep neural networks with large convolutional layers on FPGAs. By extending the hls4ml library, we demonstrate how to achieve inference latency of 5 µs using convolutional architectures, while preserving state-of-the-art model performance. Considering benchmark models trained on the Street View House Numbers Dataset, we demonstrate various methods for model compression in order to fit the computational constraints of a typical FPGA device. In particular, we discuss pruning and quantization-aware training, and demonstrate how resource utilization can be reduced by over 90% while maintaining the original model accuracy.

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Accelerated Charged Particle Tracking with Graph Neural Networks on FPGAs

Cited by 13 publications

References 26 publications

Graph Neural Networks for Charged Particle Tracking on FPGAs

Graph Neural Networks for Charged Particle Tracking on FPGAs

The Tracking Machine Learning Challenge: Accuracy Phase

Fast convolutional neural networks on FPGAs with hls4ml

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