AC IO loopback design for high speed μprocessor IO test

Provost, B.; Huang, Tian-Wei; Lim, Chee How; Tian, K.; Bashir, Muhammad; Atha, M.; Muhtaroğlu, Ali; Zhao, Cangsang; Muljono, H.

doi:10.1109/test.2004.1386933

Cited by 9 publications

(6 citation statements)

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“…In practice, only the minimum and maximum limits on phase and voltage offsets are measured, which intend to guarantee the I/O performance margin in production testing [3][4][5]. We will illustrate that such a test might not detect some chips that fail the BER specification when the random jitter (RJ) accounts for a non-trivial fraction of the total jitter (TJ).…”

Section: Figure 1 Block Diagram Of a Transceivermentioning

confidence: 99%

“…The timing margining test is performed by applying a phase offset to the clock so that it can adjust the position at which the data sample is taken. The phase position is moved either forward or backward while monitoring the pass/fail results [3][4][5].…”

Section: Limitations On Timing Margining Testmentioning

confidence: 99%

“…To alleviate these test challenges, several design-fortest (DFT) techniques have been recently proposed [3][4][5][6][7]. The most popular and efficient approach to testing a serial transceiver is based on the loopback principle, which can test most of the transceiver's functionality without relying on very expensive high-speed and high-pin-count ATE [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

“…The most popular and efficient approach to testing a serial transceiver is based on the loopback principle, which can test most of the transceiver's functionality without relying on very expensive high-speed and high-pin-count ATE [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

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An Accurate Jitter Estimation Technique for Efficient High Speed I/O Testing

Hong¹,

Cheng²

2007

16th Asian Test Symposium (ATS 2007)

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This paper describes a technique for estimating total jitter that, along with a loopback-based margining test, can be applied to test high speed serial interfaces. We first present the limitations of the existing estimation method, which is based on the dual-Dirac model. The accuracy of the existing method is extremely sensitive to the choice of the fitting region and the ratio of deterministic jitter to random jitter. Then, we propose a high-order polynomial fitting technique and demonstrate its value for a more efficient and accurate total jitter estimation at a very low Bit-Error-Rate level. The estimation accuracy is also analyzed with respect to different numbers of measurement points for fitting. This analysis shows that only a very small number (i.e., 4) of measurement points is needed for achieving accurate estimation.16th IEEE Asian Test Symposium

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Section: Figure 1 Block Diagram Of a Transceivermentioning

confidence: 99%

Section: Limitations On Timing Margining Testmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An Accurate Jitter Estimation Technique for Efficient High Speed I/O Testing

Hong¹,

Cheng²

2007

16th Asian Test Symposium (ATS 2007)

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show abstract

“…Although the two papers are about I/O leakage testing and not about CIB test, they are relevant to this paper because they avoid using a tester channel per pin. The work in [6] implements a loop back solution for testing the IOs of a microprocessor. The solution is also based on the difference in delay for state switching between different driving strengths.…”

Section: Previous Workmentioning

confidence: 99%