Abstraction techniques for validation coverage analysis and test generation

Abstract

The enormous state spaces which must be searched when verifying the correctness of, or generating tests for complex circuits, precludes the use of traditional approaches. Di cult and hard-to-nd abstractions are often required to simplify the circuits and make the problems tractable. This paper presents a simple and automatic method to extract the control ow of a circuit so that the resulting manageable state space can be explored for validation coverage analysis and automatic test generation. This control ow, capturing the essential "behavior" of the circuit, is represented as a nite state machine called the ECFM (Extracted Control Flow Machine). Simulation is currently the primary means of verifying large circuits, but an open problem is the de nition of a coverage measure for simulation vectors. We de ne functional coverage as the amount of control behavior (the ECFM) covered by the test suite, thus providing a pragmatic solution to the problem. We then combine formal veri cation techniques, using BDDs as the underlying technology, with traditional ATPG algorithms, to automatically generate additional sequences which traverse uncovered parts of the state graph of the control logic of the circuit, thus providing a means of augmenting the functional veri cation tests. Additionally, we demonstrate how the same abstraction techniques can complement traditional ATPG techniques when attacking hard-to-detect faults in the control part of the design, for which conventional ATPG techniques alone prove to be inadequate, or ine cient at best. Results on large designs show orders of magnitude improvement over conventional algorithms.

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