Abstraction-based relation mining for functional test generation

Gent, Kelson; Hsiao, Michael S.

doi:10.1109/vts.2015.7116286

Cited by 3 publications

(2 citation statements)

References 9 publications

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“…Furthermore, the search spaces of hybrid concrete and symbolic simulation techniques such as [17] and [25] are bounded to a few tens of cycles due to computational complexity, albeit far superior to traditional static symbolic execution. On the other hand, stochastic or heuristically guided search-based techniques [20,14] are often faster than semi-formal techniques and have the potential to explore a larger search space, but usually, end up producing relatively larger tests to meet similar goals.…”

Section: Introductionmentioning

confidence: 99%

RTL functional test generation using factored concolic execution

Pinto

Hsiao

2017

2017 IEEE International Test Conference (ITC)

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This thesis presents a novel concolic testing methodology and CORT, a test generation framework that uses it for high-level functional test generation. The test generation effort is visualized as the systematic unraveling of the control-flow response of the design over multiple (factored) explorations. We begin by transforming the Register Transfer Level (RTL) source for the design into a high-performance C++ compiled functional simulator which is instrumented for branch coverage. An exploration begins by simulating the design with concrete stimuli. Then, we perform an interleaved cycle-by-cycle symbolic evaluation over the concrete execution trace extracted from the Control Flow Graph (CFG) of the design. The purpose of this task is to dynamically discover means to divert the control flow of the system, by mutating primary-input stimulated control statements in this trace. We record the control-flow response as a Test Decision Tree (TDT), a new representation for the test generation effort. Successive explorations begin at system states heuristically selected from a global TDT, onto which each new decision tree resultant from an exploration is stitched.CORT succeeds at constructing functional tests for ITC99 and IWLS-2005 benchmarks that achieve high branch coverage using the fewest number of input vectors, faster than existing methods. Furthermore, we achieve orders of magnitude speedup compared to previous hybrid concrete and symbolic simulation based techniques. This work was supported in part by the DARPA CRAFT Verification Task (DARPA-BAA-15-55) and the National Science Foundation Project 1422054. This work would be incomplete without acknowledging the guidance and support of those who made it possible. To begin with, I owe my greatest thanks to my research mentor, Dr. Michael S. Hsiao for granting me the opportunity to engage in invigorating research and to participate as his research assistant. His excellent course on "Electronic Design Automation" in Spring 2016 piqued my curiosity and inspired me to pursue my Master's thesis under his tutelage. Throughout the span of the work that went into this thesis, he tirelessly guided and polished my work with his extensive background and experience in the field. I am honored to have received a chance to work with him.

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Section: Introductionmentioning

confidence: 99%

RTL functional test generation using factored concolic execution

Pinto

Hsiao

2017

2017 IEEE International Test Conference (ITC)

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“…PACOST [8] uses a formal model to generate an onion-ring guidance model for simulation. In [9] a data-mining based approach to learn supported by NSF grant 1422054 about cross cycle transitions which are used to guide the test generation towards specified target states. However, all these methods utilize macro level code coverage metrics, such as branch coverage, which do not adequately represent lower level behavior within the design.…”

Section: Introductionmentioning

confidence: 99%

Fast Multi-level Test Generation at the RTL

Gent

Hsiao

2016

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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Abstract-Functional, at-speed vectors continue to provide added value to the testing community as circuit complexity rises. Complex defects may escape traditional scan vectors and thus often require at-speed patterns. However, generation of functional/sequential vectors is an extremely challenging problem. Previous methods rely on formal models of the RTL or calls to gate level ATPG, both of which are computationally expensive, limiting the efficacy of gains made in RTL stimuli generation. In this work, we present an efficient engine for the generation of high quality functional tests at the RTL which are effective for both validation and at-speed defect detection. The proposed method utilizes a rule based, behavioral coverage metric to accurately assess the activation of circuit modules by the generated stimuli. Based on this metric, we are able to effectively generate functional test vectors at the RTL, without additional gate level information, that can achieve a high level of defect coverage and up to an order of magnitude speedup over existing techniques.

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