2019
DOI: 10.2172/1561498
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Abstract Machine Models and Proxy Architectures for Exascale Computing

Abstract: To achieve exascale computing, fundamental hardware architectures must change. The most significant consequence of this assertion is the impact on the scientific applications that run on current high performance computing (HPC) systems, many of which codify years of scientific domain knowledge and refinements for contemporary computer systems. In order to adapt to exascale architectures, developers must be able to reason about new hardware and determine what programming models and algorithms will provide the b… Show more

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Cited by 15 publications
(27 citation statements)
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“…We extend our framework to consider the case where each platform node is equipped with a (private) burst buffer. Burst buffer integration is being considered in many future HPC architectures for scalable distributed storage mechanisms and to reduce I/O contention [12,13]. Here, we study burst buffers as a mechanism to mitigate CR I/O contention from concurrent application instances.…”
Section: Burst Buffersmentioning
confidence: 99%
“…We extend our framework to consider the case where each platform node is equipped with a (private) burst buffer. Burst buffer integration is being considered in many future HPC architectures for scalable distributed storage mechanisms and to reduce I/O contention [12,13]. Here, we study burst buffers as a mechanism to mitigate CR I/O contention from concurrent application instances.…”
Section: Burst Buffersmentioning
confidence: 99%
“…A key feature of DIY2 is its ability to move data seamlessly across the memory/storage hierarchy. This feature is becoming increasingly important on HPC architectures with limited memory capacity per core but increasing number of levels of memory/storage; for example, the U.S. Department of Energy (DOE) leadership computing architectures [2].…”
Section: Out-of-core Movementmentioning
confidence: 99%
“…The Center for Exascale Simulation of Advanced Reactors (CESAR) [40], one of three co-design centers funded by the DOE, contains a suite of data analysis benchmarks called cian. 2 It exercises the main communication patterns used in many distributed-memory data analysis algorithms: neighbor exchange, merge reduction, swap reduction, and parallel sorting. The message sizes and numbers of blocks are configurable in the cian mini-app; hence, one may test a particular regime such as latency-or bandwidth-bound communication at a variety of system sizes.…”
Section: Benchmark Applicationsmentioning
confidence: 99%
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“…Motivating applications and their requirements, 2. Data structure and layout abstractions, 3. Language and compiler support for data locality, 4.…”
Section: Summary Of Findings and Recommendationsmentioning
confidence: 99%