Abnormal Silicon-Germanium (SiGe) Epitaxial Growth in FinFETs

Bhat, Talapady Srivatsa; Shintri, Shashidhar; Chen, Brad; Lo, Hsien-Ching; Peng, Jianwei; Qi, Yi; Willeman, Michael; Mishra, Shiv Kumar; Yuksek, Nuh S.; Gao, Weihong

doi:10.1109/tsm.2020.2976123

Cited by 4 publications

(3 citation statements)

References 7 publications

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“…11 and 12). First, we have analyzed the impact of an increase of the strain induced by the S/D epi in the channel (4×) what could be obtained with lower 04SP03-2 © 2024 The Japan Society of Applied Physics defective S/D epi 27,28) and hence reduced relaxation. Increasing the strain is not boosting the ON-current, as the contact resistance is acting as a bottleneck for the ON-current flow.…”

Section: Prospective Tcad Work On Potential Further Improvementsmentioning

confidence: 99%

Predictive and prospective calibrated TCAD to improve device performances in sub-20 nm gate length p-FinFETs

Eyben,

De Keersgieter,

Matagne

et al. 2024

Jpn. J. Appl. Phys.

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In this paper we present an extended analysis of the impact of SiGe p-epi source/drain engineering on sub-20nm gate length p-FinFETs performance for the N7 technology node. Different Ge concentrations and profiles (graded vs. non-graded) are evaluated making use of properly calibrated drift-diffusion TCAD simulations. Calibration of simulations is based on advanced metrology and on Monte-Carlo simulations such that the resulting simulated ID-VG (in LIN and SAT regimes) matches the one measured on device. The calibrated TCAD simulator is then used to understand the limited performances of the device and to propose new source/drain epi architectures with graded and increased Ge content. A new p-FinFET design is fabricated and tested, confirming a boost in ON-current and a reduction of the parasitic resistance. Prospective TCAD work is also presented suggesting possible future improvements on p-epi source/drain and on local interconnect contacts.

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Section: Prospective Tcad Work On Potential Further Improvementsmentioning

confidence: 99%

Predictive and prospective calibrated TCAD to improve device performances in sub-20 nm gate length p-FinFETs

Eyben,

De Keersgieter,

Matagne

et al. 2024

Jpn. J. Appl. Phys.

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“…Next, in Fig. 3 b, SiGe is epitaxial growth onto the substrate [ 32 , 33 ], followed by chemical mechanical polishing (CMP) to achieve the desired structure. Subsequently, in Fig.…”

Section: Device Structure and Operating Mechanismmentioning

confidence: 99%

Enhancing subthreshold slope and ON-current in a simple iTFET with overlapping gate on source-contact, drain Schottky contact, and intrinsic SiGe-pocket

Lin,

Cheng

2023

Discover Nano

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In this paper, we present a new novel simple iTFET with overlapping gate on source-contact (SGO), Drain Schottky Contact, and intrinsic SiGe pocket (Pocket-SGO iTFET). The aim is to achieve steep subthreshold swing (S.S) and high ION current. By optimizing the gate and source-contact overlap, the tunneling efficiency is significantly enhanced, while the ambipolar effect is suppressed. Additionally, using a Schottky contact at the drain/source, instead of ion implantation drain/source, reduces leakage current and thermal budget. Moreover, the tunneling region is replaced by an intrinsic SiGe pocket posing a narrower bandgap, which increases the probability of band-to-band tunneling and enhances the ION current. Our simulations are based on the feasibility of the actual process, thorough Sentaurus TCAD simulations demonstrate that the Pocket-SGO iTFET exhibits an average and minimum subthreshold swing of S.Savg = 16.2 mV/Dec and S.Smin = 4.62 mV/Dec, respectively. At VD = 0.2 V, the ION current is 1.81 $$\times$$ × 10–6 A/μm, and the ION/IOFF ratio is 1.34 $$\times$$ × 109. The Pocket-SGO iTFET design shows great potential for ultra-low-power devices that are required for the Internet of Things (IoT) and AI applications.

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“…Hence, an understanding of the interfacial quality of SiGe MOS capacitance (MOSCAP) structures is important. The search for treatments or fabrication methods to reduce the interface trap density (D it ) are also important in order to achieve high-performance SiGe p-channel FET technology [18][19][20][21][22][23][24][25]. In this study, the SiGe device is shown to have an abnormal C-V characteristic caused by discontinuous defects.…”

Section: Introductionmentioning

confidence: 99%

Abnormal hump in low temperature in SiGe devices with silicon capping insertion layer

Huang¹,

Chen²,

Lin³

et al. 2021

J. Phys. D: Appl. Phys.

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This study compares the capacitance-voltage (C-V) characteristics in silicon-germanium (SiGe) metal-oxide-semiconductor capacitances with and without a silicon oxide capping layer. The SiGe channel with the silicon oxide capping layer exhibits an improved C-V property at room temperature but has an abnormal shift and depression at low temperature (77 K). We determined that the threshold voltage shift was induced by the Fermi-level when ambient temperature was changed. The additional silicon capping layer was responsible for introducing defects resulting in depression and hump in the C-V measurements. Such a phenomenon is mainly caused by the different distribution of defects, which was established by modifying the alternating current pulse amplitude during the C-V measurement.

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Abnormal Silicon-Germanium (SiGe) Epitaxial Growth in FinFETs

Cited by 4 publications

References 7 publications

Predictive and prospective calibrated TCAD to improve device performances in sub-20 nm gate length p-FinFETs

Predictive and prospective calibrated TCAD to improve device performances in sub-20 nm gate length p-FinFETs

Enhancing subthreshold slope and ON-current in a simple iTFET with overlapping gate on source-contact, drain Schottky contact, and intrinsic SiGe-pocket

Abnormal hump in low temperature in SiGe devices with silicon capping insertion layer

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