ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification

Karthik, Aadithya V.; Ray, Saurabh; Nuzzo, Pierluigi; Mishchenko, Alan; Brayton, Robert K.; Roychowdhury, Jaijeet

doi:10.1109/aspdac.2014.6742898

Cited by 25 publications

(14 citation statements)

References 14 publications

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“…[22] extends the previous work by executing an onthe-fly reachability analysis to select only a sub-set of the linearized models. Simulation of non-linear analog circuits is also addressed in [20] by applying a state-space exploration technique. Continuous-time models described as a SPICE netlist are replaced by boolean finite state machines capturing the I/O behavior of the system.…”

Section: High Level Analog Modeling and Simulationmentioning

confidence: 99%

Analog Models Manipulation for Effective Integration in Smart System Virtual Platforms

Lora

Vinco

Fraccaroli

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Analog components are fundamental blocks of smart systems, as they allow a tight interaction with the environment, in terms of both sensing/actuation and communication. This impacts on the design of the overall system, and mainly on the validation phase, that thus requires the joint simulation of digital and analog aspects. In this scenario, this paper proposes the automatic conversion of analog models to C++-based languages, to remove the overhead of co-simulation with traditional virtual platform tools. The proposed methodology allows to convert a given analog description to either (1) a fully equivalent description, or (2) an abstract representation for faster simulation which models only the aspects of interest. Effectiveness and correctness have been proved on a number of case studies, that highlight the effectiveness and potentiality of the proposed methodology.

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Section: High Level Analog Modeling and Simulationmentioning

confidence: 99%

Analog Models Manipulation for Effective Integration in Smart System Virtual Platforms

Lora

Vinco

Fraccaroli

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The analog/mixed-signal circuit (in the form of SPICE netlist) is first modeled as a multi-bit digital netlist. Techniques such as in [17] may be used to automatically create such a model, where the analog values are represented using multi-bit digital codes and the non-linear continuous /…”

Section: Automated Test Quality Improvementmentioning

confidence: 99%

“…This enables us to get the list of undetected faults that can be targeted by digital ATPG to improve analog fault coverage. (d) The multilevel Boolean model generation is automated using techniques such as ABCD [17]. This enables us to automate the entire analog test generation flow.…”

Section: Figure 4 Proposed Automated Test Generation Flowmentioning

confidence: 99%

New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation

Devanathan

Balasubramanian

Parekhji

2015

2015 28th International Conference on VLSI Design

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With SOCs being increasingly designed for communication and embedded processing applications, the content of analog, mixedsignal (AMS) and RF components in them has increased. Large SOCs are often dominated by these components, which in turn also contribute to the overall incurred test time, attainable test quality and time required for silicon debug and characterisation. Existing test methods based on the use of specification based tests and use of design verification test-benches are increasingly difficult to adopt in such SOCs (as compared to standalone IP chips) since a large number of such modules and their interactions must be tested in the budgeted test time. The paper describes the practical use of fault simulation for AMS circuits to address the above issues. The main contributions of this paper are two-fold. (i) Enhancements are proposed to a commercially available analog fault simulation flow to handle specific SOC requirements of accuracy and speed, using smart management of models and/or fault lists across different fault conditions and fault sites. (ii) Efficient test generation methods targeting the analog -digital interface are built by identifying uncovered regions/operating modes of the circuit. These are novel extensions to the commercial analog EDA tools supporting regular fault simulation. Experiments are performed on industrial designs and benefits are highlighted. It is expected that such techniques will be increasingly required to be integrated into the design flows for mixed-signal SOCs.

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“…Signal and power integrity (SPI) assessment of high-speed digital communication input-output (I/O) links is important for the design analysis and verification of modern memory and chip-to-chip interfaces in order to figure out SPI problems at an early design stage [1][2][3][4][5][6][7][8][9][10][11]. The highspeed I/O link design has to also comply with certain specifications regarding the process, supply voltage, and temperature variation to obtain the target performance [12][13][14][15][16]. In fact, the temperature and power supply variations not only reduce the noise margins of digital circuits but also change the nanoscale output buffer/driver's operating point and dynamics [4,5,9,10,14].…”

Section: Introductionmentioning

confidence: 99%

Power Supply- and Temperature-Aware I/O Buffer Model for Signal-Power Integrity Simulation

Dghais

Souilem

Zayer

et al. 2018

Mathematical Problems in Engineering

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This paper presents the development and evaluation of a large-signal equivalent circuit model that accounts for the power supply fluctuation and temperature variation of I/O buffers circuit designed based on the fully depleted silicon on insulator (FDSOI) 28 nm process for signal-power integrity (SPI) simulation. A solid electrical analysis based on the working mechanisms of the nominal I/O buffer information specification- (IBIS-) like model is presented to support the derivation of an accurate and computationally efficient behavioral model that captures the essential effects of the power supply bouncing under temperature variation. The formulation and extraction of the Lagrange interpolating polynomial are investigated to extend the nominal equivalent circuit model. The generated behavioral model is implemented using the Newton-Neville’s formula and validated in simultaneous switching output buffers (SSO) scenario under temperature variation. The numerical results show a good prediction accuracy of the time domain voltage and current waveforms as well as the eye diagram of the high-speed communication I/O link while speeding-up the transient simulation compared to the transistor level model.

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ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification

Cited by 25 publications

References 14 publications

Analog Models Manipulation for Effective Integration in Smart System Virtual Platforms

Analog Models Manipulation for Effective Integration in Smart System Virtual Platforms

New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation

Power Supply- and Temperature-Aware I/O Buffer Model for Signal-Power Integrity Simulation

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