A2DTest: A complete integrated solution for on-chip ADC self-test and analysis

Mullane, Brendan; O'Brien, Vincent; MacNamee, Ciaran; Fleischmann, Thomas

doi:10.1109/test.2009.5355722

Cited by 3 publications

(1 citation statement)

References 11 publications

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“…Communication ADCs typically have stringent harmonic performance criteria and single/multi-tone tests are designed to ensure compliance. While BIST schemes with tone generation capability are used in some applications [12], ATE AWG resources are typically used for stimulus generation.…”

Section: Previous Workmentioning

confidence: 99%

Arbitrary Waveform Generator Response Shaping Method to Enable ADC Linearity Testing on Very Low Cost Automatic Test Equipment

Dasnurkar

Abraham

2011

2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop

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Mixed signal parametric testing is resource intensive and requires high-precision source and capture instrumentation to screen parametric faults. Analog to digital converters (ADC) require analog sources to provide stimulus while digital instrumentation with digital signal processing (DSP) support is used for output analysis. Precision requirements for test instrumentation are driven by the circuit under test (CUT) specifications and required to ensure minimal test escapes or excessive fallout due to source generated artifacts. Stringent accuracy requirements for the arbitrary waveform generator (AWG) modules on ATE are responsible to high hardware costs. We propose a linearity correction methodology to compensate for linearity distortion present in the analog source generator to eliminate the resulting artifacts that can cause false failures or passes. This method can be used to reduce the linearity requirement criteria for AWGs that are present in the Very-Low-Cost ATE (VLC-ATE) systems.

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Section: Previous Workmentioning

confidence: 99%

Arbitrary Waveform Generator Response Shaping Method to Enable ADC Linearity Testing on Very Low Cost Automatic Test Equipment

Dasnurkar

Abraham

2011

2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop

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ADC linearity test signal generation algorithm

Uemori

Yamaguchi

Ito

et al. 2010

2010 IEEE Asia Pacific Conference on Circuits and Systems

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A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding

Shyu

Lin

Chu

et al. 2012

IEICE Trans. Fundamentals

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Real-time on-chip measurement of bit error rate (BER) for high-speed analog-to-digital converters (ADCs) does not only require expensive multi-port high-speed data acquisition equipment but also enormous post-processing. This paper proposes a low-cost built-in-self-test (BIST) circuit for high-speed ADC BER test. Conventionally, the calculation of BER requires a high-speed adder. The presented method takes the advantages of Gray coding and only needs simple logic circuits for BER evaluation. The prototype of the BIST circuit is fabricated along with a 5-bit high-speed flash ADC in a 90-nm CMOS process. The active area is only 90 μm × 70 μm and the average power consumption is around 0.3 mW at 700 MS/s. The measurement of the BIST circuit shows consistent results with the measurement by external data acquisition equipment. key words: built-in self-test (BIST), bit error rate (BER), analog-to-digital converter (ADC)

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A2DTest: A complete integrated solution for on-chip ADC self-test and analysis

Cited by 3 publications

References 11 publications

Arbitrary Waveform Generator Response Shaping Method to Enable ADC Linearity Testing on Very Low Cost Automatic Test Equipment

Arbitrary Waveform Generator Response Shaping Method to Enable ADC Linearity Testing on Very Low Cost Automatic Test Equipment

ADC linearity test signal generation algorithm

A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding

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