A02: Concurrent operation of the processors in bit-byte CPU of a PLC

Chmiel, Mirosław; Hrynkiewicz, Edward

doi:10.1016/s1474-6670(17)30563-3

Cited by 9 publications

(12 citation statements)

References 2 publications

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“…Scan cycle, important particularly in manufacturing, can be decreased by direct execution at a dedicated processor, as shown in [39] for a Toshiba CPU. Nowadays hardware processors are designed in FPGA technology, as demonstrated by early double processor for a PLC [6] and in [42], [35] for current multicore solutions. Comparison of execution times for a few PLCs and FPGA has been presented in [18].…”

Section: Related Workmentioning

confidence: 99%

Developing a Multiplatform Control Environment

Rzońca¹,

Sadolewski²,

Stec³

et al. 2019

JAMRIS

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IEC 61131-3 control environment is called multiplatform if source programs can be executed by various processors, beginning from 8-bit microcontrollers up to 32/64bit efficient CPUs. This implies that virtual machine (VM), i.e. a software implemented processor, is used as runtime by the host CPU. The VM executes certain intermediate code into which IEC 61131-3 programs are compiled. Environment of this type called CPDev has been gradually developed by the authors over the last decade, beginning with initial report in this journal in 2008 [47]. However, technical implementations of its functionalities have not been described so far. This involves such matters as intermediate language, parametrization of the compiler and VM, multiproject runtime, translators of graphical languages, device-independent HMI, target platform and communication interfacing, which are presented in compact form in this paper. Some characteristic industrial implementations are indicated.

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Section: Related Workmentioning

confidence: 99%

Developing a Multiplatform Control Environment

Rzońca¹,

Sadolewski²,

Stec³

et al. 2019

JAMRIS

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“…There can be observed a continuous development of CPU hardware architecture and optimizations of programming technique. Researches that are carried in domain of CPU architectures show possible solution in concurrent operation of different bit-byte execution units or independent processors [3], [4]. Other approach is based on event driven triggering of program blocks that allow to save time by skipping program blocks that haven't changed since last calculation [5].…”

Section: A Program Vs Hardwarementioning

confidence: 99%

Synthesis and Implementation of Reconfigurable PLC on FPGA Platform

Milik¹,

Hrynkiewicz²

2012

International Journal of Electronics and Telecommunications

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The paper presents a set of algorithms dedicated for synthesis of reconfigurable logic controllers implemented on FPGA platform and programmed according to IEC1131 and EN61131. The program is compiled to hardware structure with a massive parallel processing. The developed method automatically allocates resources and operations. It controls resource usage and operation timing. Using mixed concept of operation allocation that considers operation timing and forms combinatorial chains of operations number of execution cycles can be reduced. An example of logic functions, PID controller and mixed arithmetic and logic programming examples are considered. Introducing the automatic implementation method allows flexible implementing the control algorithms. The maximal possible parallelism (limited only by the algorithm dependencies and available resources) is introduced.

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“…1) that together with sensors, actuators and controlled object constitutes a control system. The response time of the controller should be minimized in order to immediately react for the changes of the input conditions [2,3]. This requirements differs from a typical computing application working without direct feedback.…”

Section: Introductionmentioning

confidence: 99%

On the systematic method of conditional control program execution by a PLC

Milik

Chmiel

Hrynkiewicz

2016

Bulletin of the Polish Academy of Sciences Technical Sciences

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Abstract. The paper presents an original idea of the selective control program execution that allows significant response time reduction. The exhaustive analysis of the PLC program performance is given. An analytic approach explains the idea of the selective control program evaluation and gives the requirements for its feasibility. There is presented a systematic and formal method of program analysis based on a data flow graph approach. The method generates acyclic graph from the control program that is subject of optimization, variable allocation and instruction generation. The graph approach allows determining variables dependencies and task partitioning required by selective program execution. The method utilize the hardware supported variable changes detection. It is transparent for system operation and enables evaluation of blocks that require update.

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A02: Concurrent operation of the processors in bit-byte CPU of a PLC

Cited by 9 publications

References 2 publications

Developing a Multiplatform Control Environment

Developing a Multiplatform Control Environment

Synthesis and Implementation of Reconfigurable PLC on FPGA Platform

On the systematic method of conditional control program execution by a PLC

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